DS712 Datasheet, PDF (44/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge

INCR Write 20 Beat - Bufferable Timeout
X-Ref Target - Figure 26
LogiCORE IP AXI PLBv46 Bridge (v2.02.a)
Figure 26: INCR Write 20 Beat - Bufferable Timeout
DS712_26
DS712 July 25, 2012
www.xilinx.com
44
Product Specification