DS712 Datasheet, PDF (8/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge

LogiCORE IP AXI PLBv46 Bridge (v2.02.a)
Table 2: I/O Signal Description (Cont’d)
Port
Signal Name
Interface
I/O
Initial
State
Description
P5 S_AXI_AWBURST[1:0]⁽¹⁾
Burst type. This signal, coupled with the size information,
details how the address for each transfer within the burst
is calculated.
AXI4
I
- ^{“00“ - FIXED}
“01“ - INCR
“10“ - WRAP
“11“ - Reserved
P6 S_AXI_AWCACHE[4:0]⁽¹⁾
Cache type. This signal indicates the bufferable,
cacheable, write-through, write-back and allocate
attributes of the transaction.
Bit-0 : Bufferable (B)
AXI4
I
- _{Bit-1 : Cacheable (C)}
Bit-2 : Read Allocate (RA)
Bit-3 : Write Allocate (WA)
The combination where C=0 and WA/RA=1 are reserved.
P7 S_AXI_AWVALID
AXI4
AXI4-Lite ^I
-
Write address valid. This signal indicates that valid write
address and control information are available.
P8 S_AXI_AWREADY
AXI4
AXI4-Lite
O
Write address ready. This signal indicates that the slave
0 is ready to accept an address and associated control
signals.
AXI Write Data Channel Signals
P9
S_AXI_WDATA[C_S_AXI_
DATA_WIDTH
AXI4
I
AXI4-Lite
- Write data
P10
S_AXI_WSTB[C_S_AXI_
DATA_WIDTH/8-1:0]
AXI4
AXI4-Lite
I
-
Write strobes. This signal indicates which byte lanes in
S_AXI_WDATA are/is valid.
P11 S_AXI_WLAST⁽¹⁾
AXI4
I
-
Write last. This signal indicates the last transfer in a write
burst.
P12 S_AXI_WVALID
AXI4
I
AXI4-Lite
-
Write valid. This signal indicates that valid write data and
strobes are available.
P13 S_AXI_WREADY
AXI4
AXI4-Lite ^O
0
Write ready. This signal indicates that the slave can
accept the write data.
AXI Write Response Channel Signals
P14
S_AXI_BID[C_S_AXI_ID_
WIDTH-1:0]⁽¹⁾
Write response ID. This signal is the identification tag of
AXI4
O
0
the write response. The BID value must match the AWID
value of the write transaction to which the slave is
responding.
P15 S_AXI_BRESP[1:0]
AXI4
AXI4-Lite ^O
Write response. This signal indicates the status of the
write transaction.
“00“ - OKAY
0 _{“01“ - EXOKAY - NA}
“10“ - SLVERR - NA
“11“ - DECERR - NA
P16 S_AXI_BVALID
AXI4
O
AXI4-Lite
0
Write response valid. This signal indicates that a valid
write response is available.
P17 S_AXI_BREADY
AXI4
AXI4-Lite ^I
-
Response ready. This signal indicates that the master
can accept the response information.
DS712 July 25, 2012
www.xilinx.com
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Product Specification