DS712 Datasheet, PDF (2/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge

LogiCORE IP AXI PLBv46 Bridge (v2.02.a)
Features (continued)
• Debug register for error/timeout condition for bufferable write transfer
• Configurable (max two) number of pipelined read/write addresses
• Interrupt generation for write data strobes null
• Interrupt generation for partial data strobes except first and last data beat
• Simultaneous read and write operations
PLBv46 Master Interface Support
• Configurable (max two) number of pipelined read/write address
• Xilinx simplified PLBv46 protocol
• Single transfers of 1 to 4/8 bytes
• Fixed length of 2 to 16 data beats
• Cacheline transactions of line size 4 & 8
• Address pipelining for one read and one write
• Simultaneous read and write operations
• 32, 64, and 128-bit PLBv46 data bus widths with required data mirroring
Functional Description
Overview
A block diagram for the AXI to PLB bridge is shown in Figure 1. The PORT-2 shown in Figure 1 is valid only when
C_EN_DEBUG_REG=1, C_S_AXI_PROTOCOL=”AXI4”, and C_S_AXI_SUPPORTS_WRITE=1. The more detailed
view for the configuration is shown in Figure 2 when C_S_AXI_PROTOCOL=”AXI4” AND
C_S_AXI_SUPPORTS_WRITE=1 and C_S_AXI_SUPPORTS_READ=1.
The AXI data bus width is a 32/64-bit and the PLBv46 master is a 32/64-bit device (that is,
C_MPLB_NATIVE_DWIDTH = 32/64). PLBv46 data bus widths of 32-bit, 64-bit, and 128-bit are supported with the
AXI to PLBv46 bridge performing required data mirroring.
AXI transactions are received on the AXI slave interface and then translated to PLBv46 transactions on the PLBv46
bus through PLBv46 master interface. Both read data and write data are buffered (when
C_S_AXI_PROTOCOL=”AXI4”) in the bridge because of the mismatch of AXI and PLBv46 protocols where AXI
allows the master to throttle data flow, but the PLBv46 protocol does not allow PLB masters to throttle data flow.
The write data input from the AXI port is buffered in the bridge before the PLBv46 write transaction is initiated.
Read and write data buffer of depth 32x32/64x32 is implemented to hold the data for two PLB transfers of highest
(16) burst length. Simultaneous read and write operations from AXI to PLB are supported.
DS712 July 25, 2012
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Product Specification