DS712 Datasheet, PDF (26/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge

LogiCORE IP AXI PLBv46 Bridge (v2.02.a)
Table 10: Device Interrupt Enable Register (DIER) Bit Definitions
Bit(s)
Name
Core Reset
Access Value
Description
31- 2 Reserved
N/A
0 Reserved
DECERR Interrupt Enable
Interrupt Enable bit for routing Decode error to the System Interrupt Controller.
1
DECIE
R/W
’0’ _{’1’ = Interrupt asserts in response to DECERR}
’0’ = Interrupt does not assert in response to DECERR
SLVERR Interrupt Enable
Interrupt Enable bit for routing Slave error to the System Interrupt Controller.
0
SLVIE
R/W
’0’ _{’1’ = Interrupt asserts in response to SLVERR}
’0’ = Interrupt does not assert in response to SLVERR
Address Decoding and Memory Mapping
As AXI to PLBv46 Bridge will be a P2P interface on interconnect, address decoding is not implemented for the port
that gets translated to PLBv46. Hence, it responds to all addresses presented.
The address ranges specified by the pair of the parameters C_S_AXI_BASEADDR, C_S_AXI_HIGHADDR and
C_S_AXI_CTRL_BASEADDR, C_S_AXI_CTRL_HIGHADDR inform the interconnect about the address map of the
PLB subsystem and internal register of the bridge.
PLBv46 Remote Slave Rearbitration
The AXI to PLBv46 Bridge does not decode PLB_Mrearbitrate; the request on PLB is valid until PLB_MAddrAck
or PLB_MTimeout is asserted.
Clocking
The AXI to PLBv46 Bridge has a single clock source that supports 1:1 (AXI:PLB) clock ratio.
Reset
The AXI to PLBv46 Bridge has a single reset source. As long as the whole system (or at least PLB/AXI sides) is reset
in the same clock cycle and released in the same clock cycle, there will not be any issues.
DS712 July 25, 2012
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Product Specification