DS712 Datasheet, PDF (10/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge

LogiCORE IP AXI PLBv46 Bridge (v2.02.a)
Table 2: I/O Signal Description (Cont’d)
Port
Signal Name
Interface
I/O
Initial
State
Description
AXI Write Data Channel Signals⁽²⁾
S_AXI_CTRL_WDATA[C_S_
P34 AXI_CTRL_DATA_
AXI4-Lite I
WIDTH - 1: 0]⁽²⁾
- Write data for register interface
S_AXI_CTRL_WSTB[C_S_
P35 AXI_CTRL_DATA_
AXI4-Lite I
WIDTH/8-1:0]⁽²⁾
-
Write strobes for register interface. This signal indicates
which byte lanes to update in memory.
P36 S_AXI_CTRL_WVALID⁽²⁾
AXI4-Lite I
-
Write valid for register interface. This signal indicates that
valid write data and strobes are available.
P37 S_AXI_CTRL_WREADY⁽²⁾
AXI4-Lite O
0x0
Write ready for register interface. This signal indicates
that the slave can accept the write data.
AXI Write Response Channel Signals⁽²⁾
P38 S_AXI_CTRL_BRESP[1:0]⁽²⁾ AXI4-Lite O
Write response for register interface. This signal
indicates the status of the write transaction.
0x0 _{“00“ - OKAY}
“10“ - SLVERR
P39 S_AXI_CTRL_BVALID⁽²⁾
AXI4-Lite O
0x0
Write response valid for register interface. This signal
indicates that a valid write response is available.
P40 S_AXI_CTRL_BREADY⁽²⁾
AXI4-Lite I
Response ready for register interface. This signal
- indicates that the master can accept the response
information.
AXI Read Address Channel Signals⁽²⁾
S_AXI_CTRL_ARADDR[C_S
P41 _AXI_CTRL_ADDR_WIDTH AXI4-Lite I
-1:0]⁽²⁾
-
Read address for register interface. The read address
bus gives the address of a read transaction.
P42 S_AXI_CTRL_ARVALID⁽²⁾
AXI4-Lite I
Read address valid for register interface. This signal
-
indicates, when HIGH, that the read address and control
information is valid and remains stable until the address
acknowledgement signal, ARREDY, is high.
P43 S_AXI_CTRL_ARREADY⁽²⁾
AXI4-Lite O
Read address ready for register interface. This signal
0x1 indicates that the slave is ready to accept an address and
associated control signals.
DS712 July 25, 2012
www.xilinx.com
10
Product Specification