DS712 Datasheet, PDF (25/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge

LogiCORE IP AXI PLBv46 Bridge (v2.02.a)
Table 8: Bridge Error Address Register (BEAR) Description
Bit(s) Name Core Access Reset Value
Description
31-0
Address
(0 to 31)
R
Zeros
Transaction Address(0-31)
This value reflects the S_AXI_AWADDR at the time of error capture.
Device Global Interrupt Enable Register (DGIE)
The Device Global Interrupt Enable Register provides the final enable/disable for the interrupt output and resides
in the Register and Interrupt Module. It is a read/write register addressed at an offset 0x08 from base address
C_S_AXI_CTRL_BASEADDR. If interrupts are globally disabled (the DGIE bit is set to ’0’), there will be no
interrupt from the device under any circumstances. This is a single bit read/write register as shown in Figure 7. The
DGIE bit definitions is shown in Table 9.
.
X-Ref Target - Figure 7
2ESERVED
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Figure 7: Device Global Interrupt Enable Register
Table 9: Device Global Interrupt Enable Register (DGIE) Bit Definitions
Bit(s)
Name
Core Reset
Access Value
Description
31-1 Reserved
N/A
0 Reserved
Device Global Interrupt Enable
0
DGIE
R/W
’0’
Master Enable for routing Device Interrupt to the System Interrupt Controller.
’1’ = Enabled
’0’ = Disabled
Device Interrupt Enable Register (DIER)
The Device Interrupt Enable Register (DIER) is shown in Figure 8. It is a read/write register addressed at an offset
0x0C from base address C_S_AXI_CTRL_BASEADDR. The bit definitions of this register are shown in Table 10. The
Device Global Interrupt Enable Register provides the final enable/disable for the interrupt output to the processor
and resides in the Register and Interrupt Module. This is a single bit read/write register as shown in Figure 8. The
DIER bit definitions is shown in the Table 10.
X-Ref Target - Figure 8
2ESERVED
3,6)%

 
Figure 8: Device Interrupt Enable Register
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DS712 July 25, 2012
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Product Specification