DS712 Datasheet, PDF (18/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge

LogiCORE IP AXI PLBv46 Bridge (v2.02.a)
Table 5: AXI to PLBv46 Transaction Translation (C_S_AXI_DATA_WIDTH= 64 and
C_PLB_SMALLEST_SLAVE_SIZE = 32)
AXI Transaction
PLB Transaction
Note
INCR/FIXED Write: Burst
1 double word transfers
Bridge generates conversion
cycle on PLB This can break
into write transaction (max2)
as follows:
1. Single
2. Single, Single
The byte address bits are set based on the first byte enable that is
asserted, as required by PLB protocol.
INCR/FIXED Write: Burst
2-3 double word transfers
Bridge generates conversion
cycle on PLB and adjusts the
burst length dynamically
This can break into write
transaction (max4) as
follows:
1. Single, Single
2. Single, Single, Single
2. Single, Single, Single,
Single
3. Single, Single, Burst
4. Burst, Single, Single
5. Single, Single, Single,
Single, Single, Single
6. Burst
If all write strobes are not asserted on the first and/or last word, then
PLB singles write are performed on the first and/or last double word.
The byte address bits of the first word single PLB transaction are
set based on the first byte enable that is asserted, as required by
PLB protocol.
Address incrementing is performed as necessary to the single and
burst transaction:
1. From Single to next transfer (single or burst), address is
incremented by 0x04 and aligned to word boundary.
2. From Burst to next transfer (single), address is incremented by
length of transfer during burst, that is, (M_BE + ‘1’).
Bridge generates conversion
cycle on PLB and adjusts the
burst length dynamically
This can break into write
transaction (max5) as
INCR/FIXED Write: Burst _follows:
4-16 double word transfers _{1. Single, Single, Burst,}
Single, Single
2. Single, Single, Burst
3. Burst, Single, Single
4. Burst
If all write strobes are not asserted on the first and/or last word, then
PLB singles write are performed on the first and/or last double word.
The byte address bits of the first word single PLB transaction are
set based on the first byte enable that is asserted, as required by
PLB protocol.
Address incrementing is performed as necessary to the single and
burst transaction:
1. From Single to next transfer (single or burst), address is
incremented by 0x04 and aligned to word boundary.
2. From Burst to next transfer (single), address is incremented by
length of transfer during burst, that is, (M_BE + ‘1’).
INCR Write: Burst 17-256
double word transfers
Bridge generates conversion
cycle on PLB and adjusts the
burst length dynamically
This can break into write
transaction (max5) as
follows:
1.Single, Single, Burst(n),
Single, Single
2. Single, Single, Burst(n)
3. Burst(n), Single, Single
If all write strobes are not asserted on the first and/or last word, then
a PLB singles write is performed on the first and/or last double
word.
The byte address bits of the first word single PLB transaction are
set based on the first byte enable that is asserted, as required by
PLB protocol.
Address incrementing is performed as necessary to the single and
burst transaction:
1. From Single to next transfer (single or burst), address is
incremented by 0x04 and aligned to word boundary.
2. From Burst to next transfer (single), address is incremented by
length of transfer during burst, that is, (M_BE + ‘1’).
Read: Burst
1double word transfer
Bridge generates conversion
cycle on PLB This can break
into write transaction (max2)
as follows:
1. Single
2. Single, Single
The byte address bits are aligned to the word boundary.
INCR/FIXED Read: Burst Burst read 4-16 word
2-8 double word transfers transfers
The start address is aligned to the word boundary.
DS712 July 25, 2012
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Product Specification