DS712 Datasheet, PDF (19/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge

LogiCORE IP AXI PLBv46 Bridge (v2.02.a)
Table 5: AXI to PLBv46 Transaction Translation (C_S_AXI_DATA_WIDTH= 64 and
C_PLB_SMALLEST_SLAVE_SIZE = 32)
AXI Transaction
PLB Transaction
Note
INCR/FIXED Read: burst Burst read 16 word + Burst
9-16 double word transfers read of 2-16 word transfers
The start address is aligned to the word boundary.
INCR Read: burst 17-256
double word transfers
Burst read (17-256)*2/16
transaction + Burst read of
2-16 word transfers
The start address is aligned to the word boundary.
WRAP: 2 double word
write/read
WRAP: 4, 8 double word
write/read
Burst: 2 word write/read
4, 8 word burst write/read
Data reordering to start from address align to cache during write
and target word first during read is performed in the bridge.
WRAP: 16 double word
write/read
Two 8 word burst write/read
All wrap transfers are terminated in PLB as burst transfers. Data
reordering to start from address align to cache during write and
target word first during read is performed in the bridge.
The first transfer is from starting address with M_ABus(5) = ‘0’.
The second transfer is from starting address with M_ABus(5) = ‘1’.
AXI Write Burst Without All Write Strobes Asserted
AXI allows write strobes to be deasserted on write bursts for any data transfer. An optimization to the AXI to PLB
bridge is that it is designed to handle write strobes not all (valid bits) asserted in a given transaction only in the first
and last word of the write burst of type FIXED and INCR on AXI. The bridge assumes that the remaining (other
than first and last data beat in a transaction) are always HIGH. If either or both first and last word transfers do not
have all write strobes asserted, the PLB single transactions are performed for the first and/or last word to allow the
BE information to be passed to the PLB slave. Figure 3 shows how burst writes with write strobes not all asserted for
the first and last word are translated to the PLB-side for both INCR and FIXED type AXI burst write transactions.
AXI to PLBv46 Bridge is not validating the intermediate write strobes (only first and last are considered) during
burst; the bridge does not generate any byte mask on the PLBv46 slave interface for the address in between the
burst; this overwrites the complete 32/64-bit data on a given address irrespective how the data strobes are
generated by AXI Master.
DS712 July 25, 2012
www.xilinx.com
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Product Specification