DS712 Datasheet, PDF (7/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge

LogiCORE IP AXI PLBv46 Bridge (v2.02.a)
Table 1: Design Parameters (Cont’d)
Generic
Feature/Description
Parameter Name
PLB Parameters
G21
PLB least significant address
bus width
C_MPLB_AWIDTH
G22 PLB data width
C_MPLB_DWIDTH
G23
Native width of the master Data
Bus
C_MPLB_NATIVE_DWIDTH
Data width of the smallest slave
G24 that can talk to AXI PLBv46 C_MPLB_SMALLEST_SLAVE
bridge
G25
Define number of address
pipelines supported on PLB
C_PLB_ADDRESS_PIPELINE
Allowable
Values
Default
Values
VHDL
Type
32⁽⁴⁾
32
32, 64, 128
32
32, 64⁽⁵⁾
32
32, 64, 128
32
0
0-No address
0
pipeline
integer
integer
integer
integer
integer
Notes:
1. Valid only when C_S_AXI_PROTOCOL=”AXI4”.
2. User must assign a valid address. The bridge has address ranges based on parameter C_S_AXI_NUM_ADDR_RANGES.
3. Valid only when C_S_AXI_PROTOCOL=”AXI4” and C_EN_DEBUG_REG=1.
4. Same as C_S_AXI_ADDR_WIDTH/C_S_AXI_CTRL_ADDR_WIDTH
5. Same as C_S_AXI_DATA_WIDTH
I/O Signals
Table 2 shows the I/O signals of the AXI to PLBv46 Bridge.
Table 2: I/O Signal Description
Port
Signal Name
P1
S_AXI_AWID[C_S_AXI_ID_
WIDTH-1:0]⁽¹⁾
P2
S_AXI_AWADDR[C_S_AXI_
ADDR_WIDTH-1:0]
P3 S_AXI_AWLEN[7:0]
P4 S_AXI_AWSIZE[2:0]⁽¹⁾
Interface
I/O
Initial
State
Description
AXI Bridge Interface
AXI Write Address Channel Signals
AXI4
I
-
Write address ID. This signal is the identification tag for
the write address group of signals.
AXI4
AXI4-Lite ^I
-
AXI Write address. The write address bus gives the
address of the first transfer in a write burst transaction.
Burst length. This signal gives the exact number of
AXI4
I
- transfers in a burst
“00000000“ - “11111111” indicates Burst Length 1 - 256.
Burst size. This signal indicates the size of each transfer
in the burst.
“000“ - 1 Byte
AXI4
I
- “001“ - 2 byte (Half word)
“010“ - 4 byte (Word)
“011“ - 8 byte (Double Word)
others - NA (up to 128 bytes)
DS712 July 25, 2012
www.xilinx.com
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Product Specification