DS712 Datasheet, PDF (15/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge

LogiCORE IP AXI PLBv46 Bridge (v2.02.a)
Design Details
Bridge Transaction Translation
The PLB supported AXI transactions are directly translated to PLB. For some translations, multiple PLB
transactions must be performed. For instance, PLB does not allow a burst length of more than 16, but AXI allows up
to 256. Deasserted byte enables (BEs) during burst transfer are not allowed for PLB, but AXI does allow this. The
AXI to PLB transactions translation is shown in Table 4.
Table 4: AXI to PLB Transaction Translation
AXI Transaction
PLB Transaction
Write: Burst 1 Word, Half
Word, Byte
Single Write
Read: Burst 1 Word, Half
Word, Byte
Single Read
INCR/FIXED Write: Burst
2-16 word transfers
This can break into write
transaction (max3) as
follows:
1. Single, Single
2. Single, Single, Single
3. Single, Burst, Single
4. Single, Burst
5. Burst, Single
6. Burst
INCR/FIXED Read: burst
2-16 word transfers
WRAP: 2 word write
WRAP: 4, 8 word write
Burst read 2-16 word
transfers
Burst: 2 word write/read
4, 8 word burst write
WRAP: 16 word write
Two 8 word burst write
WRAP : 2,4,8,16 beat
Read
Aligned Wrap -
2,4,8,16 burst read
Un-aligned Wrap -
Single, Burst
Burst, Burst
Burst, Single
Note
The byte address bits are set based on the first byte enable that is
asserted, as required by PLB protocol.
The byte address bits are aligned to the word boundary.
If all write strobes are not asserted on the first and/or last word,
then a PLB single write is performed on the first and/or last word.
The byte address bits of the first word single PLB transaction are
set based on the first byte enable that is asserted, as required by
PLB protocol.
Address incrementing is performed as necessary to the single and
burst transaction:
1. From Single to next transfer (single or burst) address is
incremented by 0x04 and aligned to word boundary.
2. From Burst to next transfer (single) address is incremented by
length of transfer during burst, that is, (M_BE + ‘1’).
The start address is aligned to the word boundary.
Data reordering to start from address align to cache during write
and target word first during read is performed in the bridge.
Data reordering to start from address align to cache during write
and target word first during read is performed in the bridge.
The first transfer is from the starting address with M_ABus(5) = ‘0’.
The second transfer is from the starting address with M_ABus(5) =
‘1’.
The read on the PLB is always generated from the starting AXI
wrap address. If wrap transfer is not starting from the Wrap
bounding, the core breaks the burst transaction on the wrap
boundary.
DS712 July 25, 2012
www.xilinx.com
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Product Specification