DS712 Datasheet, PDF (17/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge

LogiCORE IP AXI PLBv46 Bridge (v2.02.a)
Table 4: AXI to PLB Transaction Translation (Cont’d)
AXI Transaction
PLB Transaction
Note
INCR Write: burst 5-16
bytes transfers
The max burst length of this
is 5 as bytes are converted
into words.
This can break into write
transaction (max3) as
follows:
1. Single, Single
2. Single, Single, Single
3. Single, Burst, Single
4. Single, Burst
5. Burst, Single
6. Burst
This is converted to word transfer by aggregating the bytes.
The byte address bits of the first word single PLB transaction are
set based on the first byte enable that is asserted, as required by
PLB protocol.
Address incrementing is performed as necessary to the single and
burst transaction:
1. From Single to next transfer, (single or burst) address is
incremented by 0x04 and aligned to word boundary.
2. From Burst to next transfer, (single) address is incremented by
length of transfer during burst, that is, (M_BE + ‘1’).
INCR Read: burst 2-16
Bytes transfers
Burst read 2-5 word
This is converted to word transfer and S_AXI_RDATA has the same
value for four S_AXI_RREADY cycles.
The max burst length of this is 5 as bytes are converted into words.
FIXED: Write/Read burst
2-16 - Half Word/Byte
Singles - Write/Read
Number of singles requested on PLB is equal to the burst length
requested by AXI
WRAP: Write/Read
1. burst 2 - Half word
2. burst 2/4 - bytes
WRAP: Write/Read
1. burst 4 - Half word
2. burst 8 - bytes
Singles - Write/Read
Burst - 2 Write/Read
Data reordering to start from address align to cache during write
and target word first during read is performed in the bridge.
WRAP: Write
1. burst 8 - Half word
2. burst 16 - bytes
4 Word Burst - Write
All wrap transfers are terminated in PLB as burst transfers.
WRAP: Write - burst 16 -
Half word
8 Word Burst - Write/Read
WRAP : 2,4,8,16 beat
Read
Aligned Burst -
2,4,8,16 burst read
Un-aligned Wrap -
Single , Burst
Burst, Burst
Burst, Single
All wrap transfers are terminated in PLB as burst transfers. The
read on the PLB is always generated from the starting AXI wrap
address. If wrap transfer is not starting from the Wrap bounding, the
core breaks the burst transaction on the wrap boundary.
Notes:
1. In AXI - INCR/FIXED write transactions, deasserted write strobes are supported only in the first and last word of the burst write.
2. All valid write strobes must to HIGH for a write WRAP transfer.
DS712 July 25, 2012
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Product Specification