DS712 Datasheet, PDF (4/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge

LogiCORE IP AXI PLBv46 Bridge (v2.02.a)
AXI4-Lite - PLBv46 Bridge
This module is not shown in the Figure 2 because it is implemented only when the AXI interface is AXI4-Lite, for
example, parameter C_S_AXI_PROTOCOL=”AXI4LITE”.
This module converts all AXI4-Lite transactions to the PLBv46 transactions.
Xfer Qual Gen (xfer_qual_gen)
Implemented only for AXI4 interface, that is, parameter C_S_AXI_PROTOCOL=”AXI4”. This module (not shown
in block diagram) is used to decode the both read and write AXI address channel.
Write Data State Machine (wr_data_sm)
Implemented only for the AXI4 interface and not read only, that is, parameters C_S_AXI_PROTOCOL=”AXI4” and
C_S_AXI_SUPPORTS_WRITE=1.
AXI can generate INCR, narrow transfers that are converted to word width to get better throughput. AXI can also
generate the WRAP transfers where the address is not align to the WRAP boundary. The sequence of this data needs
to be changed (address aligned) on PLB v46. This module generates the control signals for wr_data_fifo.
FIFO FWFT 2 Deep (fifo_fwft_2deep)
The AXI to PLBv46 Bridge design supports the deasserted data strobes (S_AXI_WSTB) in first and last data beat
only. To hold the first and last data strobe information for two transactions, FIFO of depth is used one for each data
strobe.
This is the two deep first word fall through FIFO (not shown in block diagram) is implemented using registers. This
is used in wr_data_sm to store the first_ds, last_ds.
Address FIFOs
FIFOs of depth two are used to register the write and read address channel signals.
Write Address State Machine (wr_addr_sm)
Implemented only for AXI4 interface and not read only, that is, parameters C_S_AXI_PROTOCOL=”AXI4” and
C_S_AXI_SUPPORTS_WRITE=1. This module generates the wr_request, be, size, burst for plb_wr_rd_sel and
burst_logic modules. The address is not initiated on PLB until the last data (S_AXI_WLAST) from the AXI for that
transfer is received.
Write Address Generation (wr_addr_gen)
Implemented only for AXI4 interface and not read only, that is, parameters C_S_AXI_PROTOCOL=”AXI4” and
C_S_AXI_SUPPORTS_WRITE=1. This module (not shown in block diagram) is used to generate the write address
for the PLB transfer.
Write Data FIFO (wr_data_fifo)
Implemented only for AXI4 interface and not read only, that is, parameters C_S_AXI_PROTOCOL=”AXI4” and
C_S_AXI_SUPPORTS_WRITE=1.
This is the 32x32/64x32 FIFO used to store the write data generated from AXI and is read on PLB_MWrDAck.
DS712 July 25, 2012
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Product Specification