English
Language : 

DS712 Datasheet, PDF (20/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge
LogiCORE IP AXI PLBv46 Bridge (v2.02.a)
For AXI WRAP transfer all the valid (depend on S_AXI_AWSIZE) write strobes must be HIGH.
X-Ref Target - Figure 3
!8)).#2OR&)8%$
"URSTWRITETYPE
!8)!DDRESSANDST7342"
XB
,ITTLE%NDIAN!DDRESS/FFSET
   
!8)).#2BURSTTYPE
TRANSLATIONTO0,"TRANSACTION
0,"!DDRESSAND"%
3INGLEXB
"URSTXB
"URSTLENGTH
!8)&)8%$BURSTTYPE
TRANSLATIONTO0,"TRANSACTION
0,"!DDRESSAND"%
3INGLEXB
"URSTXB
"URSTLENGTH
6ALID
6ALID
6ALID
6ALID
6ALID
6ALID
6ALID
6ALID
6ALID
6ALID
6ALID
6ALID
6ALID
6ALID
6ALID
6ALID
6ALID
6ALID
6ALID
6ALID
6ALID
6ALID
6ALID
6ALID
6ALID
6ALID
6ALID
6ALID
6ALID
6ALID
6ALID
3INGLEXB 3INGLEXB
$3?
Figure 3: AXI (32-bit) write burst type of INCR and FIXED translation to PLB (32-bit) transactions
AXI Narrow Transactions
The transaction where the size is narrower than the data width are treated as narrow transfers. If the narrow
transfer is a “FIXED” burst type, the byte address remains constant for all singles required to complete the entire
burst. If the narrow transfer is the “INCR” type, the narrow data received from AXI is collapsed to create a complete
data beat (if possible). For detail transaction translation from AXI to PLB, see Table 4.
AXI WRAP Transactions
For an optimization to the AXI to PLBv46 Bridge, all the WRAP transfers from AXI are converted as single or burst
transfer on PLBv46.
AXI allows for the target word to be any word address in the WRAP transfer. The AXI to PLBv46 Bridge performs
re-ordering of AXI target word write data to the PLB line word first write data.
For AXI WRAP reads that are not line word first, AXI to PLBv46 Bridge can generate two read requests on PLB.
For detail translation from AXI WRAP to PLB single/burst, see Table 4.
Address Pipelining
The C_S_AXI_WRITE_ACCEPTANCE and C_S_AXI_READ_ACCEPTANCE parameters define the number of
address and control information that can be buffered (max 2) for each read and write. When the ACCEPTANCE
parameter is set to 1, the next address is not accepted until the response phase and the transfer on the PLB of the first
is completed. When the ACCEPTANCE parameter is set to 2, the next address is accepted irrespective of the transfer
complete of the first. But the third address is accepted only if at least the response phase and the transfer on the PLB
of the first transaction is completed.
The AXI to PLBv46 Bridge does not support the pipelined address on the PLB. This means that the slaves that are
accessed by the AXI to PLBv46 Bridge should not respond to a secondary request (SAVALID) both for read and
write.
DS712 July 25, 2012
www.xilinx.com
20
Product Specification