DS471 Datasheet, PDF (9/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
In the case of the Read CFIFO, the HalfFull, AlmostFull, Full, and Vacancy outputs are provided to the
data stream communication interface side of the IP.
The Ch_Num signals select which channel should be the active channel for each side, respectively.
Ch_Valid indicates that the selected channel is now the active channel and that the discrete status
signals for the selected channel are valid. The Req signal indicates a request by the interface logic to
perform a data transfer with the RFIFO. The Ack signals indicate the completion of the requested
transfer. The ErrAck signals indicate an error condition has occurred.
RFIFO Channel Status
When the Bus Interface issues a status read request by asserting Bus2RFIFO_, the status bits returned
are as shown in Figure 5. The status flags (Empty, AlmostEmpty, and HalfEmpty) are contained in the
three most significant bits and the occupancy count is right justified in bits 3 to 31. If the data bus width
(C_DWIDTH) is greater than 32, the status information will always be contained in the most significant
32 bits (bit locations 0 to 31).
Figure Top x-ref 5
AlmostEmpty
0 1 2 34
31
Empty
HalfEmpty
Vacancy
Figure 5: RFIFO Channel Status Register
DS471_05_101405
Interface Pipeline Delays
Because the RFIFO is designed to be incorporated into another, higher level design, the problem of
pipeline delays associated with the request/acknowledge response has been addressed by separating
transfers into single beat and fixed length burst transfers. In a design that relies on pipelining to achieve
higher clock speeds, the latency introduced between the acknowledge and when the request signal is
deasserted can be several clock cycles.
To accommodate this latency, the RFIFO uses the state of the burst input (Bus2RFIFO_ or
Comm2RFIFO_) when the data transfer request asserts, to distinguish between single beat and burst
transfers. During status read requests on the bus side, the channel status will be placed on RFIFO2Bus_
for each clock cycle that Bus2RFIFO_ remains asserted, and the request will also be acknowledged on
each clock cycle. Assume for the remainder of this discussion that the selected channel is not empty
(bus side) or full (comm side) when the data transfer request asserts, and that it does not become empty
(or full) before the end of a burst transfer.
If the burst input is in the deasserted state at the time the data transfer request is asserted, a single data
transfer will occur, regardless of how long the request remains asserted after the acknowledge signal
(RFIFO2Bus_Ack or RFIFO2Comm_) is asserted. Figure 6 and Figure 7 show a status read and a single
beat data transfer for a read and a write, respectively, when there is a two clock delay between the
acknowledge and the deassertion of the request signal.
DS471 April 24, 2009
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Product Specification