DS471 Datasheet, PDF (22/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
Figure Top x-ref 15
Bus2WFIFO_DBus
Bus2WFIFO_Tag
WFIFO2Bus_Status
DinA _BRAM
Based
DoutA ^{Dual Port}
DoutB
AddrB
AddrA
Wr_enA
Rd_enB
Comm2WFIFO_DBus
Comm2WFIFO_Tag
Bus2WFIFO_Ch_Num
Bus2WFIFO_Burst
Bus2WFIFO_Data_WrReq
WFIFO2Bus_Status_RdReq
WFIFO2Bus_Ack
WFIFO2Bus_ErrAck
WFIFO2Bus_Ch_Valid
Write CFIFO Memory
Read/Write Controller
Write
Control
Logic
Occupancy
and Vacancy
Read
Control
Logic
Comm2WFIFO_Ch_Num
Comm2WFIFO_Burst
WFIFO2Comm_Ch_Valid
Comm2WFIFO_RdReq
WFIFO2Comm_Ack
WFIFO2Comm_ErrAck
WFIFO2Comm_HalfEmpty
WFIFO2Comm_AlmostEmpty
WFIFO2Comm_Empty
WFIFO2Comm_Occupancy
DS471_15_101405
Figure 15: Write Channel FIFO Block Diagram
WFIFO Channel Status
When the Bus Interface issues a status read request by asserting Bus2WFIFO_ Status_RdReq, the status
bits returned are as shown in Figure 16. The status flags (Full, AlmostFull, HalfFull, and Empty) are
contained in the four most significant bits and the vacancy count is right justified in bits 4 to 31. If the
data bus width (C_DWIDTH) is greater than 32, the status information will always be contained in the
most significant 32 bits (bit locations 0 to 31).
Figure Top x-ref 16
Empty
AlmostFull
0 1 2 34
31
Full HalfFull
Vacancy
Figure 16: WFIFO Channel Status
DS471_16101405
Interface Pipeline Delays
Because the WFIFO is designed to be incorporated into another, higher level design, the problem of
pipeline delays associated with the request/acknowledge response has been addressed by separating
transfers into single beat and fixed length burst transfers. In a design that relies on pipelining to achieve
higher clock speeds, the latency introduced between the acknowledge and when the request signal is
deasserted can be several clock cycles.
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DS471 April 24, 2009
Product Specification