DS471 Datasheet, PDF (28/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
Referring to Figure 21, the Bus Interface issues a status read request in clock cycle 2 and the WFIFO
responds in the same clock cycle with an acknowledge and the status, Because there is no context
switch taking place, the status value returned is hexadecimal 20000005. This value indicates that the
channel is at least half full and that there are 5 empty locations remaining in the channel.
Because the channel is not full, the Bus Interface places the data and tag information it wishes to write
on the data bus and tag field, respectively, and asserts the data write request in clock cycle 3. Because
Bus2WFIFO_Burst is deasserted, this is a single beat transfer. The WFIFO responds with an
acknowledge in cycle 3, indicating that the data will be written at the end of that cycle.
In cycle 5 the Bus Interface again asserts the status read request and the WFIFO responds with an ack
and the status value of hexadecimal 20000004, indicating that there is one less empty location
remaining in the channel. Next, the Bus Interface asserts the burst signal along with the data write
request and bursts four data words and their associated tag fields to the WFIFO. The WFIFO
acknowledges the write request in the same clock cycle, and on each clock cycle thereafter, until four
words have been transferred, at which time the acknowledge is deasserted.
For this example, the end of the data to be transmitted occurs in the last word, and the last data word
is only partially filled (zeros are used to pad in this example). Its associated tag field has the most
significant bit set, indicating that the first byte in that data word contains the last valid byte of the data
to be transmitted.¹
Finally, the Bus Interface asserts its status read request in clock cycle 13 and the WFIFO provides the
status and the acknowledge signal in the same cycle. The status value contains hexadecimal E0000000,
indicating that the channel is full, (at least) almost full, and (at least) half full, as well as there being no
vacancies remaining in the channel.
The discrete occupancy output on the Comm Interface side (WFIFO2Comm_ Occupancy) reflects this
same condition, namely that there are 255 occupied locations in the channel, the maximum number of
words it can hold.
WFIFO Read Interface Operational Description
The read port of the WFIFO is connected to the data stream communications interface logic (Comm
Interface). The Comm Interface selects the active read channel by providing a channel number on
Comm2WFIFO_ Ch_Num and ensuring that the channel is valid (WFIFO2Comm_ Ch_Valid is
asserted). The read port is activated by the assertion of Comm2WFIFO_ RdReq. Like the bus side, the
comm side of the WFIFO is also insensitive to pipeline delays associated to the request/acknowledge
interaction. If Comm2WFIFO_ Burst is deasserted when the read request asserts, only a single word
will be transferred regardless of how long the request remains asserted. If Comm2WFIFO_ Burst is
asserted when the read request asserts, then a fixed length burst will be transferred.
1. Because the tag field is user definable, the user is free to define the tag bits in any manner they choose (see
"WFIFO Tag Field" on page 33). For this example each bit in the tag field corresponds to a byte in the associated
data word. The most significant bit in the tag corresponding to the most significant byte in the data, etc. The tag
field will be all zeros for normal data words. For the last data word in a packet, the tag field will indicate which
byte is the last byte in the packet. Pad bytes in the data, if necessary, will contain zeros.
28
www.xilinx.com
DS471 April 24, 2009
Product Specification