DS471 Datasheet, PDF (23/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
To accommodate this latency, the WFIFO uses the state of the burst input (Bus2WFIFO_Burst or
Comm2WFIFO_ Burst) when the data transfer request asserts, to distinguish between single beat and
burst transfers. During status read requests on the bus side, the channel status will be placed on
WFIFO2Bus_ Status for each clock cycle that Bus2WFIFO_ Status_RdReq remains asserted, and the
request will also be acknowledged on each clock cycle. Assume for the remainder of this discussion
that the selected channel is not full (bus side) or empty (comm side) when the data transfer request
asserts and that it does not become full (or empty) before the end of a burst transfer.
If the state of the burst input is deasserted at the time the data transfer request is asserted, a single data
transfer will occur, regardless of how long the request remains asserted after the acknowledge signal
(WFIFO2Bus_Ack or WFIFO2Comm_ Ack) is asserted. Figure 17 and Figure 18 show a status read and
a single beat data transfer for a write and a read, respectively, when there is a two clock delay between
the acknowledge and the deassertion of the request signal.
Figure Top x-ref 17
Clk
Rst
Bus2WFIFO_Ch_Num[0:7]
01
Bus2WFIFO_Burst
Bus2WFIFO_Status_RdReq
Bus2WFIFO_Data_WrReq
WFIFO2Bus_Ack
WFIFO2Bus_Ch_Valid
WFIFO2Bus_ErrAck
Bus2WFIFO_DBus[0:31]
0123
4567
Bus2WFIFO_Tag[0:3]
0
WFIFO2Bus_Status[0:31]
2000
0005
Comm2WFIFO_Ch_Num[0:7]
2000
0004
01
WFIFO2Comm_Ch_Valid
Comm2WFIFO_Burst
Comm2WFIFO_RdReq
WFIFO2Comm_Ack
WFIFO2Comm_ErrAck
WFIFO2Comm_DBus[0:31]
WFIFO2Comm_Tag[0:3]
WFIFO2Comm_HalfEmpty
WFIFO2Comm_AlmostEmpty
WFIFO2Comm_Empty
WFIFO2Comm_Occupancy[0:7]
FA
FB
cycle 1
2
3
4
5
6
7
8
9
10
11
DS471_17_101405
Figure 17: WFIFO Single Beat Write Timing With ACK Delay
DS471 April 24, 2009
www.xilinx.com
23
Product Specification