DS471 Datasheet, PDF (5/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
Channel FIFO Parameters
Parameter List
The CFIFO design supports user configurability via a set of design parameters implemented as VHDL
input Generics. The generics for the RFIFO are listed in Table 1 and for the WFIFO in Table 2. It is
important to note the ID Number Column. This ID will be used interchangeably with the Parameter
name in this document.
Table 1: RFIFO Parameter List.
Read
Generic
Feature / Description
Parameter Name
Allowable Values
Default
Value
VHDL
Type
RG1
RG2
RG3
RG4
RG5
FIFO Memory Sizing
Number of channels in the
CFIFO
C_NUM_
CHANNELS
1 to 256
Total number of words
contained in the CFIFO
C_TOTAL_DEPTH
Virtex: 4 to 4096
FIFO word data width in bits
C_DWIDTH
32 to 256⁽¹⁾
Feature Selection
Bus side fixed length burst
size
C_BUS_BURST_
SIZE
0 to 256
0 or 1 indicates that
bursts are disabled
for the bus side.
Comm side fixed length
burst size
C_COMM_BURST
_SIZE
0 to 256
0 or 1 indicates that
bursts are disabled
for the comm side.
Target FPGA Family Selection
32
16384
32
8
8
Positive
Positive
Positive
Natural
Natural
RG6
User Target FPGA Family
selection
C_FAMILY
virtex: Use Virtex
block RAM memo-
ry core
String
Notes:
1. This parameter would normally be sized to match the width of the host processor bus (that is, 32, 64, 128, etc.).
The width of the FIFO memory array will be C_DWIDTH + (C_DWIDTH / 8) to allow a tag to be associated with
each word of data and to provide storage for FIFO status information.
DS471 April 24, 2009
www.xilinx.com
5
Product Specification