DS471 Datasheet, PDF (30/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
The Comm Interface has access to discrete status information, so there is no status read request on this
side. Because the discrete empty flag is deasserted to begin with, the Comm Interface issues a read
request in clock cycle 2 and the WFIFO responds with the data and tag field and an acknowledge in
clock cycle 3.¹ The discrete occupancy output changes at the end of cycle 3 indicating that there is one
less occupied location in the channel. Because Comm2WFIFO_ Burst was deasserted this is a single
beat transfer.
The empty indicator is still deasserted and the occupancy count indicates that there are four words left
in this channel. So the Comm Interface issues another read request in cycle 5, this time with the burst
signal asserted, and in cycle 6 the WFIFO acknowledges with the next data word and its associated tag
field. The burst continues until four words have been transferred and the WFIFO deasserts the
acknowledge signal. WFIFO2Comm_ AlmostEmpty asserted in cycle 9, indicating that only one word
remains in the channel. In cycle 10 the empty discrete output is asserted indicating that the channel is
empty. The discrete occupancy output reflects the state of the channel after each word is read and
indicates that there are no more occupied locations within the channel.
As in the previous write operation example, the tag field is used to indicate an end-of-packet condition.
For this example, the last byte of the packet is contained in the last word written to the WFIFO. As the
Comm Interface reads the data it monitors the tag field associated with each data word. When a bit in
the tag field is set, indicating that the end of the data has been reached, the Comm Interface uses the tag
field to identify the byte within the last word that is the last byte to be transmitted. In this example, the
first byte is marked with the end-of-packet, and the remaining bytes are padding. The Comm Interface
would only transmit bytes up to, and including, that last byte, ignoring the padding bytes.
WFIFO Channel Number Context Switch Operational Description
When either of the channel number inputs to the WFIFO change, an internal context switch occurs in
which the status and state of the previous channel are saved, and the status and state of the new
channel must be retrieved, loaded, and output to the appropriate port. This context switch takes several
clock cycles to complete.
During the context switch initiated by a channel number change on the communications side, the
discrete status outputs emitted by the WFIFO on the communications side become invalid as the
previous channel’s status is replaced by the new channel’s status. The channel valid signal
(WFIFO2Comm_ Ch_Valid) indicates when the context switch has completed and that the new discrete
status outputs are valid. The channel valid signal also indicates that data transfers can take place on
that channel. On the local bus side, a context switch will typically delay the assertion of the
acknowledge signal for the first status read or data write transfer.
The length of the delay for either the bus side or the comm side is affected by several factors, including
a context switch occurring at the same time on the opposite side, or a long burst transfer taking place on
the opposite side. The best case delay for a context switch is three clock cycles. The worst case delay is
directly related to burst length on the opposite side. A long burst size on one side can potentially delay
a context switch on the other side for the entire length of the burst, plus the time needed for the context
switch, if the context switch occurs at or near the start of the burst. Therefore, although the WFIFO can
accommodate any reasonable burst size in the range specified for C_BUS_BURST_ SIZE and
C_COMM_BURST_ SIZE, the user is urged to use the smallest burst size that meets their needs to
minimize the latency of context switches.
1. The delay from the assertion of the request to the assertion of the acknowledge on the read side of the FIFO is
due to the extra clock cycle required when reading from the internal memory.
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DS471 April 24, 2009
Product Specification