DS471 Datasheet, PDF (31/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
For a context switch to take place correctly, the channel number is only allowed to change at the end
of a clock cycle in which all request signals are deasserted (Bus2WFIFO_Data_WrReq and
Bus2WFIFO_ Status_RdReq for the Bus Interface side, or Comm2WFIFO_ RdReq for the Comm
Interface side). Changing the channel number on a side where a request signal is asserted may produce
incorrect behavior in the WFIFO.
WFIFO Context Switch Operation Example
Figure 23 illustrates the timing associated with a channel number context switch on both the write and
read sides of the WFIFO. For this example we will assume that the bus side was on channel 2 and the
communications side was on channel 3 and that they both change to channel 1 at the same time.
Channel 1 contains a single word at first and the Bus Interface performs a write burst of four words and
then changes to channel 5. The Comm Interface side performs a single beat read and then performs a
burst read of the final four words.
After changing the channel number to channel 1, WFIFO2Bus_Ch_Valid negates and the Bus Interface
asserts the status read request in clock cycle 2. Because this status request immediately follows a
channel number change, it is delayed by two clocks as the context switch takes place.
WFIFO2Bus_Ch_Valid asserts and the WFIFO acknowledges in cycle 4 with a status of 000000FE,
indicating that all but one location are vacant. The Bus Interface performs a write burst of four words,
followed by another status read request in cycle 10. Because this last status request does not occur
during a context switch the Bus Interface side of the WFIFO responds in the same clock cycle. This last
status value of 000000FB indicates that all but four locations are vacant. Finally the Bus Interface
changes its channel number to channel 5 and immediately requests a status read in cycle 11, which
takes three clocks to complete because it occurs during the context switch.
As the Bus Interface is changing to channel 1, the Comm Interface changes its channel number to
channel 1 also and waits for the assertion of the channel valid signal. The status signals on the Comm
Interface side of the WFIFO become unknown during clock cycles 2 and 3 because of the context switch.
The channel valid signal is asserted in cycle 4, indicating that the status for channel 1 is valid and that
read transfers are allowed.
The Comm Interface observes that there is one word in the channel and so asserts its read request for a
single beat read in cycle 4 and the WFIFO responds with an acknowledge and the data in cycle 5. In
cycle 8 the Comm Interface again asserts its read request, this time with the burst signal asserted, for a
four word burst transfer. The WFIFO responds with the data and an acknowledgement in cycles 10
through 13.
Figure 24 shows a context switch in which the Comm Interface changes to channel 1 at the same time as
a burst is starting on the Bus Interface side. The context switch on the comm side is delayed by the burst
on the bus side.
DS471 April 24, 2009
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Product Specification