DS471 Datasheet, PDF (34/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
Normally, data that is not at the end of the packet is stored with a tag field of all zeros. When the Bus
Interface is ready to write the last word of a packet for the current channel, it modifies the tag field for
that word and asserts the write request. The data and tag field are stored in the WFIFO. When the
Comm Interface reads data from the WFIFO, it uses the tag field to determine when it has reached the
end-of-packet for that channel. The definition of the bits in the tag field is user defined and should be
specified in the IP core that utilizes a WFIFO.
Write CFIFO Signal Interface
I/O Signal Summary
Table 5 defines the Write CFIFO I/O signal set. Some ports have widths that are Parameter setting
dependent. The dependent widths are referenced to the Parameter ID values defined in Table 1 on page
5.
Table 5: Write Channel CFIFO Interface Signals
Write
Port
Signal Name
Width
Interface I/O
Signal Description
WP1
WP2
WP3
WP4
WP5
WP6
WP7
WP8
WP9
WP10
Clk
Rst
Bus2WFIFO_Ch_
Num
Bus2WFIFO_Burst
Bus2WFIFO_Data
_WrReq
Bus2WFIFO_
Status_RdReq
WFIFO2Bus_Ack
WFIFO2Bus_
ErrAck
Bus2WFIFO_DBus
Bus2WFIFO_Tag
System
Bus
I
Bus
I
Local Bus Interface
(0:get_chnl_widt
h(WG1)-1)
Bus
I
Bus
I
Bus
I
Bus
I
Bus
O
(0:WG3-1)
Bus
O
Bus
I
(0:WG3/8-1)
Bus
I
Input Synchronization clock from the IP
Active high reset signal from the IP
Indicates which channel should be
active for write transactions.
Indicates that a data write request is for
a fixed length burst.
This active high input signals the WFIFO
that the local bus interface is requesting
a write data transfer to the active
channel. ⁽¹⁾
This active high input signals the WFIFO
that the local bus interface is requesting
a read status transfer from the active
channel. ⁽¹⁾
When asserted, this active high output
indicates that the requested transfer will
be performed on the next rising edge of
the Clk.
When asserted, this active high output
indicates that the local bus interface
tried to write to a full channel.
The input data bus. Data is written to
memory on each rising Clk while WP7 is
asserted.
Tag field associated with the data word
being written. The tag field is written to
memory on each rising Clk while WP7 is
asserted.
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DS471 April 24, 2009
Product Specification