DS471 Datasheet, PDF (8/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
Vacancy/Occupancy Width Function
get_occ_width(num_channels, total_num_bytes, data_bus_width: positive) return positive;
get_vac_width(num_channels, total_num_bytes, data_bus_width: positive) return positive;
The get_occ_width and get_vac_width functions require three positive integer arguments. The first
argument contains the number of channels in the CFIFO and the second argument contains the total
number of words in the CFIFO memory array. The third argument contains the width of the CFIFO
data buses (typically C_DWIDTH). They return a positive integer that specifies the width of a signal
containing all allowable occupancy/vacancy values for a single channel in the CFIFO.
Read CFIFO Functional Description
RFIFO Block Diagram
The main requirement of the Read Channel FIFO is to provide a receive data buffer function between
the data stream communication logic and the local bus interface logic in an IP core. The Block Diagram
for the Read CFIFO is shown in Figure 4. The data input (write) interface is connected to the data
stream communication side and the data output (read) interface is connected to the local bus interface
side. The module design is centered around Dual Port Block Memory core (block RAMs) memory
elements. Access to the memory core is facilitated by the Memory Read/Write Controller block.
This block is composed of three major functions: Write Control, Read Control, and the
Occupancy/Vacancy calculation. The input (write) side of the RFIFO is controlled by the Write Control
Logic which includes such things as a write address counter and the memory write controls. The Read
Control Logic block provides the timing and signal interface between the memory core read port and
the local bus Interface of the IP. The Occupancy/Vacancy Calculation Block is tasked with the
continuous update of the HalfFull, AlmostFull, Full, and the Vacancy discrete status outputs for the
currently active channel.
Figure Top x-ref 4
Comm2RFIFO_DBus
DinA
DoutB
RRFIFO_DBus
BRAM
AddrA Based AddrB
Dual Port
Wr_enA
Rd_enB
Comm2RFIFO_Ch_Num
Comm2RFIFO_Burst
RFIFO2Comm_Ch_Valid
Comm2RFIFO_WrReq
RFIFO2Comm_Ack
RFIFO2Comm_ErrAck
RFIFO2Comm_HalfFull
RFIFO2Comm_AlmostFull
RFIFO2Comm_Full
RFIFO2Comm_Vacancy
Read CFIFO Memory
Read/Write Controller
Write
Control
Logic
Occupancy
and Vacancy
Read
Control
Logic
Bus2RFIFO_Ch_Num
Bus2RFIFO_Burst
Bus2RFIFO_Data_RdReq
Bus2RFIFO_Status_RdReq
RFIFO2Bus_Ack
RFIFO2Bus_ErrAck
RFIFO2Bus_Ch_Valid
Figure 4: Read Channel FIFO Block Diagram
DS471_04_101405
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DS471 April 24, 2009
Product Specification