DS471 Datasheet, PDF (16/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
In cycle eight, the Bus Interface again asserts the status read request and the RFIFO responds with an
ack and the status value of hexadecimal 00000004, indicating that there are four words of data in the
channel. The Bus Interface keeps its status read request asserted in clock cycle 9 and the RFIFO
provides the status and the acknowledge signal in the same cycle. The status value contains
hexadecimal 00000005, indicating that there are five valid words of data in the channel.
The discrete vacancy output on the Comm Interface side (RFIFO2Comm_) reflects this same condition,
namely that there are 250 vacant locations in the channel.
Figure 11 shows a similar operation of the Comm Interface writing to the RFIFO, but it depicts the
condition when the RFIFO becomes full. The discrete RFIFO2Comm_ is asserted, RFIFO2Comm_
asserts when the RFIFO2Comm_ is one, and RFIFO2Comm_ asserts when RFIFO2Comm_ is zero. Also
the status values read by the Bus Interface reflect the that the FIFO has an occupancy of 254 and 255
words, respectively.
RFIFO Read Interface Operational Description
The read port of the RFIFO is connected to the local bus interface (Bus Interface). The Bus Interface
selects the active read channel by providing a channel number on Bus2RFIFO_Ch_Num. The read port
is activated by the assertion of Bus2RFIFO_ or Bus2RFIFO_Data_RdReq.
If a read status transfer is being requested, the RFIFO will complete a context switch if necessary, and
place the channel status word on the data bus and assert RFIFO2Bus_Ack.
In the case of a read data transfer, if data exists in the channel buffer (the Empty bit in the status word
is zero), and any context switch has completed, the RFIFO will place the data on the data bus
(RFIFO2Bus_) and assert RFIFO2Bus_Ack. If a read data request to an empty channel is detected by the
RFIFO, RFIFO2Bus_ will be asserted and the state of that channel will not change. Figure 5 shows the
locations of the status bits in the channel status word for the RFIFO.
Bus Interface Read Operation Example
For this example assume both the Bus Interface and the Comm Interface have channel one selected and
the most recent context switch on either side has completed and both channel numbers are stable. The
channel number is eight bits in width, reflecting the fact that there are 256 channels numbered 0 to 255,
and the discrete vacancy output on the Comm side is also eight bits wide, indicating that each channel
can hold 255 (m – 1) words. We will also assume that no transfers occur on the Comm Interface side,
and, for clarity, during this discussion we will assume there are no pipeline delays associated with the
request/acknowledge logic.
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DS471 April 24, 2009
Product Specification