DS471 Datasheet, PDF (35/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
Table 5: Write Channel CFIFO Interface Signals (Contd)
Write
Port
Signal Name
Width
Interface I/O
Signal Description
WP11
WFIFO2Bus_
Status
(0:WG3-1)
The output data bus for status reads.
Bus
O Status is valid only when WP7 is
asserted.
WP12
WFIFO2Bus_Ch_
Valid
When asserted, this active high output
Bus
O
indicates that the bus channel is now
valid and data transfers can be
performed.
Comm Interface
WP13
Comm2WFIFO_
Ch_Num
(0:get_chnl_widt
h(WG1)-1)
Comm
I
Indicates which channel should be
active for read transactions.
WP14
Comm2WFIFO_
Burst
Comm
I
Indicates that a read request is for a
fixed length burst.
WP15
WFIFO2Comm_
Ch_Valid
Comm
When asserted, this active high output
O indicates that status for the active
channel is valid.
WP16
Comm2WFIFO_
RdReq
Comm
This active high input signals the WFIFO
I
that the comm interface is requesting a
read data transfer from the active
channel. ⁽¹⁾
WP17
WFIFO2Comm_
Ack
Comm
When asserted, this active high output
O
indicates that the requested read data
transfer will be performed on the next
rising edge of the Clk.
WP18
WFIFO2Comm_
ErrAck
Comm
When asserted, this active high output
O indicates the comm interface tried to
read from and empty channel.
WP19
WFIFO2Comm_
DBus
(0:WG3-1)
Comm
O
The output data bus. Data is valid only
when WP17 is asserted.
WP20
WFIFO2Comm_
Tag
(0:WG3/8-1)
Comm
Tag field associated with the data word
O being read. It is only valid when WP17 is
asserted.
WP21
WFIFO2Comm_
HalfEmpty
Comm
When asserted, this active high output
O indicates that the active channel is half
empty.
WP22
WFIFO2Comm_
AlmostEmpty
Comm
When asserted, this active high output
O indicates that only one word remains in
the active channel.
DS471 April 24, 2009
www.xilinx.com
35
Product Specification