DS471 Datasheet, PDF (11/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
Figure Top x-ref 7
Clk
Rst
Bus2RFIFO_Ch_Num[0:7]
Bus2RFIFO_Status_RdReq
Bus2RFIFO_Burst
Bus2RFIFO_Data_RdReq
RFIFO2Bus_Ack
RFIFO2Bus_ErrAck
RFIFO2Bus_Ch_Valid
RFIFO2Bus_DBus[0:31]
Comm2RFIFO_Ch_Num[0:7]
RFIFO2Comm_Ch_Valid
Comm2RFIFO_Burst
Comm2RFIFO_WrReq
RFIFO2Comm_Ack
RFIFO2Comm_ErrAck
Comm2RFIFO_DBus[0:31]
RFIFO2Comm_HalfFull
RFIFO2Comm_AlmostFull
RFIFO2Comm_Full
RFIFO2Comm_Vacancy[0:7]
Cycle
E0000000
01234567
FF
1
2
01
60000001
01
FE
3
4
Figure 7: RFIFO Single Beat Write Timing with ACK Delay
5
DS471_07_101405
If fixed length bursts are enabled (C_BUS_BURST_ SIZE or C_COMM_BURST_SIZE are greater than
one), then, if the burst input (Bus2RFIFO_ or Comm2RFIFO_) is asserted when the request asserts, the
RFIFO will perform a fixed length burst transfer, transferring data on each clock cycle, until the number
of words specified for the burst size have been transferred.
The acknowledge (RFIFO2Bus_Ack or RFIFO2Comm_) will deassert after the last word and the RFIFO
will wait for the request to deassert before accepting another transfer request. Figure 8 and Figure 9
show the timing for a status read request followed by a fixed length burst transfer of four words for a
read and a write, respectively, with a two clock delay between the acknowledge and the request
deassertion.
DS471 April 24, 2009
www.xilinx.com
11
Product Specification