DS471 Datasheet, PDF (15/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
Figure Top x-ref 11
Clk
Rst
Bus2RFIFO_Ch_Num[0:7]
Bus2RFIFO_Status_RdReq
Bus2RFIFO_Burst
Bus2RFIFO_Data_RdReq
RFIFO2Bus_Ack
RFIFO2Bus_ErrAck
RFIFO2Bus_Ch_Valid
RFIFO2Bus_DBus[0:31]
Comm2RFIFO_Ch_Num[0:7]
RFIFO2Comm_Ch_Valid
Comm2RFIFO_Burst
Comm2RFIFO_WrReq
RFIFO2Comm_Ack
RFIFO2Comm_ErrAck
Comm2RFIFO_DBus[0:31]
RFIFO2Comm_HalfFull
RFIFO2Comm_AlmostFull
RFIFO2Comm_Full
RFIFO2Comm_Vacancy[0:7]
Cycle
0000
00FA
1111
1111
05
1
2
01
0000
00FE
01
2222
2222
3333
3333
4444
4444
5555
5555
04
03
02
01
3
4
5
6
7
Figure 11: RFIFO Write Timing to Fill the FIFO
00000
00FF
00
8
9
DS471_11_101405
Referring to Figure 10, the Bus Interface issues a status read request in the second clock cycle and the
RFIFO responds in the same clock cycle with an acknowledgement and the status because there is no
context switch taking place. The status value returned is hexadecimal E0000000, indicating that the
channel is empty (and at least almost empty, and at least half empty), corresponding to the occupancy
count of 0 which indicates that there is no data in the channel.
Because the Comm Interface has access to discrete status information, there is no status read request on
this side. The assertion of RFIFO2Comm_ indicates that the channel is ready and the discrete status
outputs are stable. Because the channel is not full, the Comm Interface places the data it wishes to write
on the data bus and asserts the data write request in clock cycle two. The RFIFO responds with an
acknowledge in cycle two, indicating that the data will be written at the end of that cycle. Because the
burst signal was deasserted at the time the write request asserted, this is a single beat transfer.
In cycle five, the Comm Interface asserts the data write request with the burst signal asserted and bursts
four data words to the RFIFO. The RFIFO acknowledges the write request on the each clock cycle, until
four words have been written. This is a fixed length burst, and that the RFIFO will terminate the burst
by deasserting RFIFO2Comm_ after the fourth data transfer is complete, even if Comm2RFIFO_
remains asserted.
DS471 April 24, 2009
www.xilinx.com
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Product Specification