DS471 Datasheet, PDF (14/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
A transfer acknowledge (RFIFO2Comm_) to the Comm Interface is generated by the RFIFO indicating
that the requested write operation will complete on the next rising edge of the clock signal. When the
currently active channel in the RFIFO becomes full (indicated by RFIFO2Comm_ asserted), any further
write requests will be ignored and an error acknowledge (RFIFO2Comm_) will be asserted. Further
attempts to write to that channel will produce error acknowledgements until one or more read transfers
have occurred from the read side.
In addition to the full flag, there are two other status flags (RFIFO2Comm_ and RFIFO2Comm_) as well
as a vacancy count (RFIFO2Comm_) that the Comm Interface can monitor. These status flags are only
valid while RFIFO2Comm_ is asserted.
Communications Interface Write Operation Example
For this example assume both the Bus Interface and the Comm Interface have channel one selected and
the most recent context switch on either side has completed and both channel numbers are stable. The
channel number is eight bits in width, reflecting the fact that there are 256 channels numbered from 0 to
255, and the discrete vacancy output on the communications side is also eight bits in width, indicating
each channel can hold 255 (m – 1) words. We will also assume that C_COMM_BURST_SIZE is set to 4
(fixed length bursts of four words) and that no data transfers occur on the Bus Interface side during this
discussion. Also, for clarity, we will assume there are no pipeline delays associated with the
request/acknowledge logic.
Figure Top x-ref 10
Clk
Rst
Bus2RFIFO_Ch_Num[0:7]
Bus2RFIFO_Status_RdReq
Bus2RFIFO_Burst
Bus2RFIFO_Data_RdReq
RFIFO2Bus_Ack
RFIFO2Bus_ErrAck
RFIFO2Bus_Ch_Valid
RFIFO2Bus_DBus[0:31]
Comm2RFIFO_Ch_Num[0:7]
RFIFO2Comm_Ch_Valid
Comm2RFIFO_Burst
Comm2RFIFO_WrReq
RFIFO2Comm_Ack
RFIFO2Comm_ErrAck
Comm2RFIFO_DBus[0:31]
RFIFO2Comm_HalfFull
RFIFO2Comm_AlmostFull
RFIFO2Comm_Full
RFIFO2Comm_Vacancy[0:7]
Cycle
E000
0000
0123
4567
FF
1
2
01
0000
0004
0000
0005
01
89AB
CDEF
1122
3344
5566
7788
9900
0000
FE
3
4
FD
FC
FB
5
6
7
8
FA
9
10
DS471_10_101405
Figure 10: RFIFO Write Timing
14
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DS471 April 24, 2009
Product Specification