DS471 Datasheet, PDF (12/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
Figure Top x-ref 8
Clk
Rst
Bus2RFIFO_Ch_Num[0:7]
Bus2RFIFO_Status_RdReq
Bus2RFIFO_Burst
Bus2RFIFO_Data_RdReq
RFIFO2Bus_Ack
RFIFO2Bus_ErrAck
RFIFO2Bus_Ch_Valid
RFIFO2Bus_DBus[0:31]
Comm2RFIFO_Ch_Num[0:7]
RFIFO2Comm_Ch_Valid
Comm2RFIFO_Burst
Comm2RFIFO_WrReq
RFIFO2Comm_Ack
RFIFO2Comm_ErrAck
Comm2RFIFO_DBus[0:31]
RFIFO2Comm_HalfFull
RFIFO2Comm_AlmostFull
RFIFO2Comm_Full
RFIFO2Comm_Vacancy[0:7]
Cycle 1
20000004
FB
234
01
89AB
CDEF
1122
3344
5566
7788
01
9900
0000
E00000000
FC FD FE
FF
5 6 7 8 9 10 11 12 13 14 15
DS471_08_101405
Figure 8: RFIFO Fixed Length Burst Read Timing With ACK Delay
12
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DS471 April 24, 2009
Product Specification