DS471 Datasheet, PDF (17/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
Figure Top x-ref 12
Clk
Rst
Bus2RFIFO_Ch_Num[0:7]
Bus2RFIFO_Status_RdReq
Bus2RFIFO_Burst
Bus2RFIFO_Data_RdReq
RFIFO2Bus_Ack
RFIFO2Bus_ErrAck
RFIFO2Bus_Ch_Valid
RFIFO2Bus_DBus[0:31]
2000
0005
0123
4567
Comm2RFIFO_Ch_Num[0:7]
RFIFO2Comm_Ch_Valid
Comm2RFIFO_Burst
Comm2RFIFO_WrReq
RFIFO2Comm_Ack
RFIFO2Comm_ErrAck
Comm2RFIFO_DBus[0:31]
RFIFO2Comm_HalfFull
RFIFO2Comm_AlmostFull
RFIFO2Comm_Full
RFIFO2Comm_Vacancy[0:7]
FA
Cycle 1
2
3
4
01
2000
0004
89AB
CDEF
1122
3344
5566
7788
9900
0000
E000
0000
01
FB
FC
FD
FE
FF
5
6
7
8
9
10 11 12 13
DS471_12_101405
Figure 12: RFIFO Read Timing
See Figure 12 during the discussion of this example. The Bus Interface issues a status read request in the
second clock cycle and the RFIFO responds in the same clock cycle with an acknowledgement and the
status because there is no context switch taking place. The status value returned is hexadecimal
00000005, indicating an occupancy count of 5 words with none of the status flags asserted. Because the
RFIFO is not empty, the Bus Interface issues a read request in clock cycle three and the RFIFO responds
with the data and an acknowledge in clock cycle four. The discrete vacancy output also changes in cycle
four to indicate that there is one additional vacant location in the channel. Because the read request
asserted when the burst signal was deasserted, this is a single beat transfer.
In cycle six, the Bus Interface again asserts the status read request and the RFIFO responds with an ack
and the status value of hexadecimal 00000004, indicating that there are four words of data in the
channel. The empty flag is still deasserted so the Bus Interface issues another read request in cycle
seven, this time with the burst signal asserted, and in cycle eight the RFIFO acknowledges with the next
data word. Because the RFIFO is capable of providing data on each clock cycle for fixed length bursts,
the Bus Interface leaves its read request asserted, bursting the data from the RFIFO. In cycle twelve, the
Bus Interface again asserts the status read request and the RFIFO responds with an ack and the status
value of hexadecimal E0000000, indicating that all Empty flags are asserted and there is no data in the
RFIFO.
DS471 April 24, 2009
www.xilinx.com
17
Product Specification