DS471 Datasheet, PDF (6/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
Table 2: WFIFO Parameter List
Write
Generic
Feature / Description
Parameter Name
Allowable
Values
Default VHDL
Value Type
FIFO Memory Sizing
WG1
Number of channels in the
CFIFO
C_NUM_CHANNELS
1 to 256
32
Positive
WG2
Total number of words
contained in the CFIFO
C_TOTAL_DEPTH
Virtex: 4 to 4096 16384 Positive
WG3
FIFO word data width in
bits
C_DWIDTH
32 to 256⁽¹⁾
32
Positive
Feature Selection
0 to 256
WG4
Bus side fixed length burst
size
C_BUS_BURST_
SIZE
0 or 1 indicates
that bursts are
8
Natural
disabled on the
bus side.
0 to 256
WG5
Comm side fixed length
burst size
C_COMM_BURST_
SIZE
0 or 1 indicates
that bursts are
8
Natural
disabled on the
comm side.
Target FPGA Family Selection
WG6
User Target FPGA Family
selection
C_FAMILY
virtex: Use Vir-
tex block RAM
memory core
String
Notes:
1. This parameter would normally be sized to match the width of the host processor bus (that is, 32, 64, 128, etc.).
The width of the FIFO memory array will be C_DWIDTH + (C_DWIDTH / 8) to allow a tag to be associated with
each word of data and to provide storage for FIFO status information.
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DS471 April 24, 2009
Product Specification