DS471 Datasheet, PDF (20/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
Read CFIFO Signal Interface
I/O Signal Summary
Table 4 defines the Read CFIFO I/O signal set implementation. Some ports are variable width based
upon input parameter settings. The Parameter dependent widths are specified using the Parameter
Number indicated in Table 1 on page 5.
Table 4: Read Channel FIFO Interface Signals
Read
Port
Signal Name
Width
Interface I/O
Signal Description
System
RP1 Clk
Bus
I Input Synchronization clock from the IP
RP2 Rst
Bus
I
Active high master reset signal from the
IP
Local Bus Interface
RP3
Bus2RFIFO_Ch_ (0:get_chnl_wid
Num
th(RG1)-1)
Bus
I
Indicates which channel should be
active for read transactions.
RP4
Bus2RFIFO_
Burst
Bus
I
Indicates that a data read request is for
a fixed length burst.
RP5
Bus2RFIFO_Data
_RdReq
This active high input signals the RFIFO
Bus
I
that the local bus interface is requesting
a read data transfer from the active
channel. ⁽¹⁾
RP6
Bus2RFIFO_
Status_RdReq
This active high input signals the RFIFO
Bus
I
that the local bus interface is requesting
a read status transfer from the active
channel. ⁽¹⁾
RP7 RFIFO2Bus_Ack
When asserted, this active high output
Bus
O
indicates that the requested data or
status transfer will be performed on the
next rising edge of the Clk.
RP8
RFIFO2Bus_
ErrAck
When asserted, this active high output
Bus
O indicates that a read data transfer was
attempted from an empty channel.
RFIFO2Bus_
RP9
DBus
(0:RG3-1)
Bus
O
The output data bus. Data is valid only
when RP7 is asserted.
RP10
RFIFO2Bus_
Ch_Valid
RP11
RP12
Comm2RFIFO_
Ch_Num
Comm2RFIFO_
Burst
Bus1
O
Comm Interface
(0:get_chnl_wid
th(RG1)-1)
Comm
I
Comm
I
When asserted, this active high output
indicates that the bus channel is now
valid and data transfers can be
performed.
Indicates which channel should be
active for write transactions.
Indicates that a data write request is for
a fixed length burst.
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DS471 April 24, 2009
Product Specification