DS471 Datasheet, PDF (3/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
Figure Top x-ref 1
channel n - 1
channel 2 data(m - 2)
FIFO
Depth
channel 1
channel 2
channel 0
channel 2 data(2)
channel 2 data(1)
channel 2 data(0)
channel 2 status
Figure 1: CFIFO with n Channels
ds471_01_101405
Figure Top x-ref 2
IPCore
OPB
IPIF
Valid
status
data
Tag
Chnl #
Burst
WrReq
Local Bus
Interface
Logic
RdReq
Ack
Chnl #
Burst
DataReq
StatusReq
Ack
data
Valid
discrete
status lines
data
Tag
WFIFO ^{Chnl #}
Valid
Burst
Req
Ack
Data Stream
Communication
Chnl #
Burst
Interface
Logic
Valid
Req
RFIFO
Ack
data
discrete
status lines
Data
Stream
Figure 2: WFIFO and RFIFO Instantiation in an IP Core
DS471_02_101405
Channel FIFO Overview
Channel FIFO Status Calculation
The status calculation in a normal FIFO implementation is based on the relative differences between the
write address and the read address. This process is graphically shown in Figure 3.
DS471 April 24, 2009
www.xilinx.com
3
Product Specification