DS471 Datasheet, PDF (10/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
Figure Top x-ref 6
Clk
Rst
Bus2RFIFO_Ch_Num[0:7]
01
Bus2RFIFO_Status_RdReq
Bus2RFIFO_Burst
Bus2RFIFO_Data_RdReq
RFIFO2Bus_Ack
RFIFO2Bus_ErrAck
RFIFO2Bus_Ch_Valid
RFIFO2Bus_DBus[0:31]
20000005
01234567
20000004
Comm2RFIFO_Ch_Num[0:7]
01
RFIFO2Comm_Ch_Valid
Comm2RFIFO_Burst
Comm2RFIFO_WrReq
RFIFO2Comm_Ack
RFIFO2Comm_ErrAck
Comm2RFIFO_DBus[0:31]
RFIFO2Comm_HalfFull
RFIFO2Comm_AlmostFull
RFIFO2Comm_Full
RFIFO2Comm_Vacancy[0:7]
FA
FB
Cycle 1
2
3
4
5
6
7
8
9
10
11
12
DS471_06_101405
Figure 6: RFIFO Single Beat Read Timing With ACK Delay
10
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DS471 April 24, 2009
Product Specification