DS471 Datasheet, PDF (27/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
If bursts are enabled (C_BUS_BURST_ SIZE is greater than zero) then, a burst transfer occurs when
Bus2WFIFO_Data_WrReq asserts while Bus2WFIFO_Burst is asserted. The WFIFO will accept
C_BUS_BURST_ SIZE number of words and then terminate the transfer (by deasserting
WFIFO2Bus_Ack), regardless of the state of Bus2WFIFO_Data_WrReq and Bus2WFIFO_Burst. The
write request must be deasserted and then reasserted to begin a new transfer.
If the Bus Interface attempts to write data to a full channel, the WFIFO will assert an error acknowledge
(WFIFO2Bus_ ErrAck) rather than the transfer acknowledge and the state of the channel will not
change.
Bus Interface Write Operation Example
For this example assume both the Bus Interface and the Comm Interface have channel 1 selected and
the most recent context switch on either side has completed and both channel numbers are stable. The
channel number is eight bits in width, reflecting the fact that there are 256 channels numbered from 0 to
255, and the discrete occupancy output is also eight bits wide, reflecting the fact that each channel can
hold 255 (m – 1) words. We will also assume that C_BUS_BURST_ SIZE is set to 4, no pipeline delays
exist, and that no data transfers occur on the Comm Interface side during this discussion.
Figure Top x-ref 21
Clk
Rst
Bus2WFIFO_Ch_Num[0:7]
01
Bus2WFIFO_Burst
Bus2WFIFO_Status_RdReq
Bus2WFIFO_Data_WrReq
WFIFO2Bus_Ack
WFIFO2Bus_ErrAck
WFIFO2Bus_Ch_Valid
Bus2WFIFO_DBus[0:31]
0123
4567
89AB
CDEF
1122
3344
5566
7788
9900
0000
55AA
55AA
Bus2WFIFO_Tag[0:3]
0
0
0
0
8
F
WFIFO2Bus_Status[0:31]
2000
0005
2000
0004
E000
0000
Comm2WFIFO_Ch_Num[0:7]
01
WFIFO2Comm_Ch_Valid
Comm2WFIFO_Burst
Comm2WFIFO_RdReq
WFIFO2Comm_Ack
WFIFO2Comm_ErrAck
WFIFO2Comm_DBus[0:31]
WFIFO2Comm_Tag[0:3]
WFIFO2Comm_HalfEmpty
WFIFO2Comm_AlmostEmpty
WFIFO2Comm_Empty
WFIFO2Comm_Occupancy[0:7]
FA
FB
FC FD FE
FF
cycle 1
2
3
4
5
6
7
8
9 10 11 12 13 14
DS471_21_101405
Figure 21: WFIFO Write Timing
DS471 April 24, 2009
www.xilinx.com
27
Product Specification