DS471 Datasheet, PDF (29/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
If data exists in the channel buffer (WFIFO2Comm_ Empty is deasserted), the WFIFO will place the
data on the data bus (WFIFO2Comm_ DBus) and the tag field associated with that data on the tag port
(WFIFO2Comm_ Tag) and assert WFIFO2Comm_ Ack. If a read request to an empty channel is
detected by the WFIFO, WFIFO2Comm_ ErrAck will be asserted instead of WFIFO2Comm_ Ack, and
the state of that channel will not change. Two additional status flags (WFIFO2Comm_ HalfEmpty and
WFIFO2Comm_ AlmostEmpty), plus an optional occupancy count (WFIFO2Comm_ Occupancy), are
available to the Comm Interface for monitoring the state of the WFIFO.
Communications Interface Read Operation Example
For this example assume both the Bus Interface and the Comm Interface have channel 1 selected and
the most recent context switch on either side has completed and both channel numbers are stable. On
the Comm Interface side, the assertion of WFIFO2Comm_ Ch_Valid indicates that the channel is ready
and the discrete status outputs are stable. The channel number is eight bits in width, reflecting the fact
that there are 256 channels numbered 0 to 255, and discrete occupancy output is also eight bits wide,
reflecting the fact that each channel can hold 255 (m – 1) words. We will also assume that
C_COMM_BURST_ SIZE is set to 4, no pipeline delays exist, and that no data transfers occur on the Bus
Interface side during this discussion. See Figure 22 during the discussion of this example.
Figure Top x-ref 22
Clk
Rst
Bus2WFIFO_Ch_Num[0:7]
01
Bus2WFIFO_Burst
Bus2WFIFO_Data_WrReq
Bus2WFIFO_Status_RdReq
WFIFO2Bus_Ack
WFIFO2Bus_ErrAck
WFIFO2Bus_Ch_Valid
Bus2WFIFO_DBus[0:31]
Bus2WFIFO_Tag[0:3]
WFIFO2Bus_Status[0:31]
Comm2WFIFO_Ch_Num[0:7]
0000
00FF
01
WFIFO2Comm_Ch_Valid
Comm2WFIFO_Burst
Comm2WFIFO_RdReq
WFIFO2Comm_Ack
WFIFO2Comm_ErrAck
WFIFO2Comm_DBus[0:31]
0123
4567
WFIFO2Comm_Tag[0:3]
0
89AB
CDEF
0
1122
3344
0
5566
7788
0
9900
0000
8
WFIFO2Comm_HalfEmpty
WFIFO2Comm_AlmostEmpty
WFIFO2Comm_Empty
WFIFO2Comm_Occupancy[0:7]
05
04
03
02
01
00
cycle 1
2
3
4
5
6
7
8
9
10 11 12 13
DS471_22_101405
Figure 22: WFIFO Read Timing
DS471 April 24, 2009
www.xilinx.com
29
Product Specification