DS471 Datasheet, PDF (36/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
Table 5: Write Channel CFIFO Interface Signals (Contd)
Write
Port
Signal Name
Width
Interface I/O
Signal Description
WP23
WFIFO2Comm_
Empty
Comm
When asserted, this active high output
O indicates that the active channel is
empty.
WP24
WFIFO2Comm_
Occupancy
(0:get_occ_width
(WG1,WG2,WG3
)-1)
Comm
O
Notes:
1. Read or write transfer aborts are not supported in the CFIFO.
Indicates the number of words
remaining in the active channel.
System Build Considerations
Platform Builder
The Channel FIFO modules are incorporated as sub-designs of an IP core. The generics supplied to the
CFIFOs are set (either directly or derived) from the settings of the input generics of the top design
module of the IP instantiating a CFIFO.
Version Compatibility
This is the initial parameterized version of the design so there are no previous versions.
Design Implementation
Tools
• VHDL Design Entry: Text editor.
• VHDL Compilation and Simulation: ModelSim
• Logic Synthesis: Xilinx XST.
• Place and Route: Xilinx Design Manager
• Documentation Graphics: Adobe FrameMaker 7.2, Version 7.2bp144
• Documentation Timing Diagrams: SynaptiCAD Timing Diagrammer Pro, Version 7.9
• Documentation Text: FrameMaker 7.2, Version 7.2bp144
Target Technology
The CFIFO designs are compatible with selected Xilinx Virtex-4 and Spartan-3 device architectures.
Specification Exceptions
There are no known specification exceptions at this time.
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DS471 April 24, 2009
Product Specification