DS471 Datasheet, PDF (24/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
Figure Top x-ref 18
Clk
Rst
Bus2WFIFO_Ch_Num[0:7]
Bus2WFIFO_Burst
Bus2WFIFO_Data_WrReq
Bus2WFIFO_Status_RdReq
WFIFO2Bus_Ack
WFIFO2Bus_ErrAck
WFIFO2Bus_Ch_Valid
Bus2WFIFO_DBus[0:31]
Bus2WFIFO_Tag[0:3]
WFIFO2Bus_Status[0:31]
Comm2WFIFO_Ch_Num[0:7]
WFIFO2Comm_Ch_Valid
Comm2WFIFO_Burst
Comm2WFIFO_RdReq
WFIFO2Comm_Ack
WFIFO2Comm_ErrAck
WFIFO2Comm_DBus[0:31]
WFIFO2Comm_Tag[0:3]
WFIFO2Comm_HalfEmpty
WFIFO2Comm_AlmostEmpty
WFIFO2Comm_Empty
WFIFO2Comm_Occupancy[0:7]
cycle 1
0123
4567
0
05
2
3
4
01
0000
00FF
01
89AB
CDEF
0
1122
3344
0
5566
7788
0
9900
0000
8
04
03
02
01
00
5
6
7
8
9
10 11 12 13
DS471_18_101405
Figure 18: WFIFO Single Beat Read Timing With ACK Delay
If fixed length bursts are enabled (C_BUS_BURST_ SIZE or C_COMM_BURST_ SIZE are greater than
one), then, if the burst input (Bus2WFIFO_Burst or Comm2WFIFO_ Burst) is asserted when the request
asserts, the WFIFO will perform a fixed length burst transfer, transferring data on each clock cycle, until
the number of words specified for the burst size have been transferred. The acknowledge
(WFIFO2Bus_Ack or WFIFO2Comm_ Ack) will deassert after the last word and the WFIFO will wait
for the request to deassert before accepting another transfer request. Figure 19 and Figure 20 show the
timing for a status read request followed by a fixed length burst transfer of four words for a write and
a read, respectively, with a two clock delay between the acknowledge and the request deassertion.
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DS471 April 24, 2009
Product Specification