DS471 Datasheet, PDF (26/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
Figure Top x-ref 20
Clk
Rst
Bus2WFIFO_Ch_Num[0:7]
Bus2WFIFO_Burst
Bus2WFIFO_Data_WrReq
Bus2WFIFO_Status_RdReq
WFIFO2Bus_Ack
WFIFO2Bus_ErrAck
WFIFO2Bus_Ch_Valid
Bus2WFIFO_DBus[0:31]
Bus2WFIFO_Tag[0:3]
WFIFO2Bus_Status[0:31]
Comm2WFIFO_Ch_Num[0:7]
WFIFO2Comm_Ch_Valid
Comm2WFIFO_Burst
Comm2WFIFO_RdReq
WFIFO2Comm_Ack
WFIFO2Comm_ErrAck
WFIFO2Comm_DBus[0:31]
WFIFO2Comm_Tag[0:3]
WFIFO2Comm_HalfEmpty
WFIFO2Comm_AlmostEmpty
WFIFO2Comm_Empty
WFIFO2Comm_Occupancy[0:7]
cycle 1
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3344
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7788
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DS471_20_101405
Figure 20: WFIFO Fixed Length Burst Read Timing With ACK Delay
WFIFO Write Interface Operational Description
Data to be transmitted by the IP core is transferred from the local bus interface logic to the data stream
communications interface logic via the Write Channel FIFO (WFIFO). The input (write port) of the
WFIFO is connected to the local bus interface side of the IP (Bus Interface).
During a typical data transmit operation, the Bus Interface specifies a channel number
(Bus2WFIFO_Ch_Num) to the WFIFO and then requests a status read from that channel by asserting
Bus2WFIFO_ Status_RdReq. The WFIFO responds by loading the channel status information onto
WFIFO2Bus_ Status and asserting WFIFO2Bus_Ack. If the channel is not full, the Bus Interface loads
data into the write port of the WFIFO (Bus2WFIFO_DBus) and the tag information associated with the
data into the tag port (Bus2WFIFO_Tag). The write to the WFIFO is initiated by asserting
Bus2WFIFO_Data_WrReq.
As mentioned earlier, during data transfers the state of Bus2WFIFO_Burst determines the length of the
transfer. If Bus2WFIFO_Burst is deasserted when the data write request asserts, only one word will be
transferred (WFIFO2Bus_Ack will assert for only one clock cycle), regardless of how long the request
remains asserted.
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DS471 April 24, 2009
Product Specification