DS471 Datasheet, PDF (19/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
Because Comm2RFIFO_ was asserted for this request, the additional 3 data words are written to
channel 2 of the RFIFO.
On the local bus side, a context switch will typically delay the assertion of the acknowledge signal for
the first read data transfer. However, if the first read transfer is a status read then the status will be
available in two clock cycles following the request.
An example of a context switch on the Bus Interface is shown in Figure 14. In this example, the Bus
Interface completes its activity on channel 1 and then switches to channel 2. RFIFO2Bus_ negates as the
context switch begins. Bus2RFIFO_ is asserted to obtain the status of channel 2 and the context switch
occurs. RFIFO2Bus_ asserts 3 clocks later and the status is returned, due to the context switching.
Because the status of hex 0000000A indicates that there is data in the RFIFO, the Bus Interface asserts
Bus2RFIFO_ and Bus2RFIFO_Data_RdReq and performs a burst read of 4 words. Because the context
switch occurred during the status read, the first data word of the burst is returned one clock after the
read request and all subsequent words are returned each clock cycle thereafter. When the Bus Interface
has concluded its read burst, it then reads the status of the channel.
Figure Top x-ref 14
Clk
Rst
Bus2RFIFO_Ch_Num[0:7]
Bus2RFIFO_Status_RdReq
Bus2RFIFO_Burst
Bus2RFIFO_Data_RdReq
RFIFO2Bus_Ack
RFIFO2Bus_ErrAck
RFIFO2Bus_Ch_Valid
RFIFO2Bus_DBus[0:31]
Comm2RFIFO_Ch_Num[0:7]
RFIFO2Comm_Ch_Valid
Comm2RFIFO_Burst
Comm2RFIFO_WrReq
RFIFO2Comm_Ack
RFIFO2Comm_ErrAck
Comm2RFIFO_DBus[0:31]
RFIFO2Comm_HalfFull
RFIFO2Comm_AlmostFull
RFIFO2Comm_Full
RFIFO2Comm_Vacancy[0:7]
01
0000
0005
02
0000
000A
01
89AB
CDEF
1122
3344
5566
7788
9900
0000
0000
0006
FA
Figure 14: Bus Interface Context Switch
DS471_14_011405
DS471 April 24, 2009
www.xilinx.com
19
Product Specification