DS471 Datasheet, PDF (2/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
Features (contd)
• FIFO-like status outputs on communications interface side of HalfFull, AlmostFull, and Full for
Read Channel FIFO, and HalfEmpty, AlmostEmpty, and Empty for Write Channel FIFO, in
addition to true Occupancy (Write Channel FIFO) and Vacancy (Read Channel FIFO) outputs.
• A Tag field input to Write CFIFO is stored in a memory array on every write data transfer. This field
is user definable and is intended to provide a mechanism for indicating which byte within a word
is the last valid byte in a packet.
• Write and Read Ports on each CFIFO are synchronized to a common clock source (synchronous
operation).
Functional Description
A Channel FIFO (CFIFO) is used as a data buffering element within an IP core in which multiple
channels within a data stream, generated at one rate, must be buffered before being consumed at a later
time and possibly at a different rate¹ and/or different order. A typical application might be interfacing
a processor bus to a physical communication data stream in which multiple channels coexist. Figure 1
shows a CFIFO containing n channels, where each channel contains m – 1 data words, and one status
word. To compute m, the FIFO depth is divided by N, where N is the smallest integral power of two
greater than or equal to n. This means that if n is not an integral power of two, portions of the FIFO
memory will be unused.
Each channel includes a status word that contains information about the state of that channel. The state
information includes the occupancy count for that channel, and information necessary to allow the
CFIFO control logic to perform a context switch when a new channel is selected. In essence, each
channel within a CFIFO operates as an independent, m – 1 word FIFO selectable via the channel
number.
Figure 2 shows a hypothetical IP core in which both a write CFIFO (WFIFO) and a read CFIFO (RFIFO)
have been instantiated. This hypothetical core incorporates a processor bus interface via the OPB IPIF
(On-chip Peripheral Bus Intellectual Property InterFace) module and transmits and receives data to
and from its communication data stream. The IP core provides registers for the status information, and
address decoding, to allow the host processor to read the status as well as write to the WFIFO and read
from the RFIFO. The IP core also provides the clock and reset signals for both CFIFOs.
1. This is not meant to imply different clock frequencies, only that the time required to consume the data my be
different than the time required to supply it. For example, the processor may fill a write channel FIFO using
fixed length burst transfers on the Bus Interface side, while the Comm Interface side uses single beat transfers
to send the data. In this case the rate at which the FIFO is filled is much faster than the rate at which it is emp-
tied.
2
www.xilinx.com
DS471 April 24, 2009
Product Specification