DS471 Datasheet, PDF (4/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
Figure Top x-ref 3
Memory
Difference here
determines Full
Condition and Occupancy
Write Address Pointer
Difference here
determines Empty
Condition and Occupancy
Read Address Pointer
DS471_03_101405
Figure 3: FIFO Occupancy / Vacancy Calculation
For the channel FIFO the same status calculation is performed on each channel rather than the entire
memory array. So for a channel FIFO there are n status calculations, where n is the number of
channels.Because only the status of the currently active channel is necessary, only that status is
provided to the IP core. When a new channel is selected, the previous channel’s status must be saved
and the new channel’s status must be loaded. This context switch requires several clocks before the
CFIFO can begin transferring data.
The CFIFOs are designed to context switch whenever the channel number changes. A channel number
is allowed to change in any clock cycle in which the request (read or write) signals for that side of
the CFIFO have been deasserted for at least one clock cycle. The context switch has completed when
the channel valid signal is asserted and/or the status read (on the bus side of the CFIFO) has been
acknowledged. The new channel’s discrete status output bits (on the data stream communications side
of the CFIFO) will be valid when the channel valid signal is detected asserted.
On the local bus interface side of the IP, a status read request can occur in the same clock cycle that the
channel number changes. The acknowledgement for the status request indicates that the context switch
to the new channel has completed, the status from the memory array is valid, and that data transfer
requests are allowed. At that time a new data transfer can be requested. If it is not desired to read the
status to determine when a context switch to a new channel has completed, the channel valid signal can
be sampled. The context switch has completed when the channel valid signal is asserted. At that time,
a new data transfer can be requested. Once a context switch has completed, the CFIFOs can supply data
on each clock cycle of a fixed length burst.
The length of a burst can be different for each side and is set by a generic. To minimize the latency
introduced by a context switch, the CFIFOs will perform a context switch as soon as possible after
detecting a channel number change, as long as no transfer request is asserted. Any additional clock
cycles an IP designer can introduce between a channel number change and a status/data transfer
request reduces the latency between the request and the acknowledgement.
The CFIFOs are designed to be insensitive to pipeline delays associated with request deassertion
during burst transfers. The CFIFO will terminate a burst transfer once the correct number of words
have been transferred, regardless of how long the request remains asserted after the last acknowledge.
The request must be deasserted before a new transfer can begin. Also large burst sizes on one side of the
CFIFO can significantly increase the time required for a context switch on the other side.
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DS471 April 24, 2009
Product Specification