DS471 Datasheet, PDF (25/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
Figure Top x-ref 19
ClK
Rst
Bus2WFIFO_Ch_Num[0:7]
Bus2WFIFO_Burst
Bus2WFIFO_Status_RdReq
Bus2WFIFO_Data_WrReq
WFIFO2Bus_Ack
WFIFO2Bus_ErrAck
WFIFO2Bus_Ch_Valid
Bus2WFIFO_DBus[0:31]
Bus2WFIFO_Tag[0:3]
WFIFO2Bus_Status[0:31]
Comm2WFIFO_Ch_Num[0:7]
WFIFO2Comm_Ch_Valid
Comm2WFIFO_Burst
Comm2WFIFO_RdReq
WFIFO2Comm_Ack
WFIFO2Comm_ErrAck
WFIFO2Comm_DBus[0:31]
WFIFO2Comm_Tag[0:3]
WFIFO2Comm_HalfEmpty
WFIFO2Comm_AlmostEmpty
WFIFO2Comm_Empty
WFIFO2Comm_Occupancy[0:7]
cycle 1
01
20000004
89AB 1122
CDEF 3344
0
0
5566
7788
0
9900
0000
8
01
E0000000
FB
234
FC FD FE
FF
5 6 7 8 9 10 11 12 13 14 15
DS471_19_101405
Figure 19: WFIFO Fixed Length Burst Write Timing With ACK Delay
DS471 April 24, 2009
www.xilinx.com
25
Product Specification