DS471 Datasheet, PDF (21/37 Pages) Xilinx, Inc – Channel FIFO

Channel FIFO (CFIFO) (v1.00a)
Table 4: Read Channel FIFO Interface Signals (Contd)
Read
Port
Signal Name
Width
Interface I/O
Signal Description
RP13
RFIFO2Comm_
Ch_Valid
RP14
Comm2RFIFO_
WrReq
Comm
Comm
When asserted, this active high output
O indicates that status for the active
channel is valid.
This active high input signals the RFIFO
I
that the comm interface is requesting a
write data transfer to the active channel.
(1)
RP15
RFIFO2Comm_
Ack
Comm
O
RP16
RFIFO2Comm_
ErrAck
Comm
O
RP17
Comm2RFIFO_
DBus
(0:RG3-1)
Comm
I
RP18
RFIFO2Comm_
HalfFull
Comm
O
RP19
RFIFO2Comm_
AlmostFull
Comm
O
RP20
RFIFO2Comm_
Full
Comm
O
RP21 ^RFIFO2Comm_
(0:get_vac_widt
h(RG1,RG2,RG
Comm
O
Vacancy
3)-1)
Notes:
1. Read or write transfer aborts are not supported in the CFIFO.
When asserted, this active high output
indicates that the requested data
transfer will be performed on the next
rising edge of the Clk.
When asserted, this active high output
indicates that the Comm interface
attempted to write to a full channel.
The input data bus. Data is written to
memory on each rising Clk while RP15
is asserted.
When asserted, this active high output
indicates that half of the locations in the
active channel are occupied.
When asserted, this active high output
indicates that only one empty location
remains in the active channel.
When asserted, this active high output
indicates that the active channel is full.
Indicates the number of empty locations
remaining in the active channel.
Write Channel FIFO Functional Description
WFIFO Block Diagram
The Block Diagram for the Write CFIFO is shown in Figure 15. The module design is very similar to that
of the Read CFIFO. However, the sense of the data transfer is in the opposite direction to that of the
Read CFIFO. Also, the WFIFO contains an additional tag field for use in marking the end of data within
a channel data word. The Read Control Logic provides the interface between the data stream
communications interface in the IP and the read side of the FIFO. The Write Control Logic interfaces
with the local bus interface in the IP. The Occupancy/Vacancy Calculation Block is similar to the same
function in the RFIFO except that the HalfEmpty, AlmostEmpty, Empty, and Occupancy discrete
outputs are provided to the communications interface of the IP.
DS471 April 24, 2009
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21
Product Specification