DS791 Datasheet, PDF (8/46 Pages) Xilinx, Inc – LogiCORE IP AXI Controller

LogiCORE IP AXI Controller Area Network (axi_can) (v1.03.a)
The width of some of the AXI CAN device signals depends on parameters selected in the design. The dependencies
between the AXI CAN device design parameters and I/O signals are shown in Table 4.
Table 4: Parameter Port Dependencies
Generic
or Port
Name
Affects
Depends
Relationship Description
Design Parameters
G3 C_S_AXI_HIGHADDR
G2
Address range pair dependency
G7 C_S_AXI_ADDR_WIDTH
P3, P13
Defines the width of the ports
G8 C_S_AXI_DATA_WIDTH
P6, P7, P16
Defines the width of the ports
I/O Signals
P3
S_AXI_AWADDR[C_S
_AXI_ADDR_WIDTH- 1:0]
-
G7
Port width depends on the generic
C_S_AXI_ADDR_WIDTH.
P6
S_AXI_WDATA[C_S_
AXI_DATA_WIDTH - 1: 0]
-
G8
Port width depends on the generic
C_S_AXI_DATA_WIDTH.
P7
S_AXI_WSTB[C_S_
AXI_DATA_WIDTH/8- 1:0]
-
G8
Port width depends on the generic
C_S_AXI_DATA_WIDTH.
P13
S_AXI_ARADDR[C_S
_AXI_ADDR_WIDTH - 1:0]
-
G7
Port width depends on the generic
C_S_AXI_ADDR_WIDTH.
P16
S_AXI_RDATA[C_S_AXI_DATA
_WIDTH -1:0]
-
G8
Port width depends on the generic
C_S_AXI_DATA_WIDTH.
Operational Modes
The CAN controller supports these modes of operation:
• Configuration
• Normal
• Sleep
• Loop Back
Table 5 contains the CAN Controller modes of operation and the corresponding control and status bits. Inputs that
affect the mode transitions are discussed in Configuration Register Descriptions, page 13.
Table 5: CAN Controller Modes of Operation
S_AXI_ SRST
ARESET Bit
_N
(SRR)
CEN
Bit
(SRR)
LBACK SLEEP
Bit
Bit
(MSR) (MSR)
CONFIG
Status Register Bits (SR)
(Read Only)
LBACK SLEEP NORMAL
Operation Mode
‘0’
X
X
X
X
‘1’
‘0’
‘0’
‘0’
Core is Reset
‘1’
‘1’
X
X
X
‘1’
‘0’
‘0’
‘0’
Core is Reset
‘1’
‘0’
‘0’
X
X
‘1’
‘0’
‘0’
‘0’
Configuration
Mode
‘1’
‘0’
‘1’
‘1’
X
‘0’
‘1’
‘0’
‘0’
Loop Back Mode
‘1’
‘0’
‘1’
‘0’
‘1’
‘0’
‘0’
‘1’
‘0’
Sleep Mode
‘1’
‘0’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
Normal Mode
DS791 June 22, 2011
www.xilinx.com
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Product Specification