DS791 Datasheet, PDF (3/46 Pages) Xilinx, Inc – LogiCORE IP AXI Controller

LogiCORE IP AXI Controller Area Network (axi_can) (v1.03.a)
Protocol Engine
The CAN protocol engine consists primarily of the Bit Timing Logic (BTL) and the Bit Stream Processor (BSP)
modules. Figure 2 illustrates a block diagram of the CAN protocol engine.
X-Ref Target - Figure 2
To / From
Object Layer
TX
Message
Control /
Status
RX
Message
CAN Protocol
Engine
TX Bit
TX
Bit Stream
Control _{Bit Timing}
CAN
PHY
RX Bit
Logic
RX
Processor
Sampling
Clock
BRPR
Clock
Prescaler
CAN CLK
DS649_02_091007
Figure 2: CAN Protocol Engine
Bit Timing Logic
The primary functions of the Bit Timing Logic (BTL) module include:
• Synchronizing the CAN controller to CAN traffic on the bus
• Sampling the bus and extracting the data stream from the bus during reception
• Inserting the transmit bitstream onto the bus during transmission
• Generating a sampling clock for the BSP module state machine
X-Ref Target - Figure 3
TS1
TS2
Sync
Segment
Propagation
Segment
Phase
Segment 1
Phase
Segment 2
DS791_03_100701
Figure 3: CAN Bit Timing
As illustrated in Figure 3, the CAN bit time is divided into four parts:
• Sync segment
• Propagation segment
• Phase segment 1
• Phase segment 2
These bit time parts are comprised of a number of smaller segments of equal length called time quanta (tq). The
length of each time quantum is equal to the quantum clock time period (period = tq). The quantum clock is
generated internally by dividing the incoming oscillator clock by the baud rate pre-scaler. The pre-scaler value is
passed to the BTL module through the Baud Rate Prescaler (BRPR) register.
DS791 June 22, 2011
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