DS791 Datasheet, PDF (19/46 Pages) Xilinx, Inc – LogiCORE IP AXI Controller

LogiCORE IP AXI Controller Area Network (axi_can) (v1.03.a)
Error Status Register
The Error Status Register (ESR) indicates the type of error that has occurred on the bus. If more than one error
occurs, all relevant error flag bits are set in this register. The ESR is a write-to-clear register. Writes to this register
does not set any bits, but does clear the bits that are set.
Table 17 shows the bit positions in the ESR and Table 18 provides ESR bit descriptions. All the bits in the ESR are
cleared when a '0' is written to the CEN bit in the SRR.
Table 17: Error Status Register BIT Positions
0 — 26
27
28
29
30
31
Reserved
ACKER
BERR
STER
FMER
CRCER
Table 18: Error Status Register Bit Descriptions
Bit(s)
Name
Core
Access
Default
Value
0—26
Reserved Read/Write
0
27
ACKER Write to Clear
0
28
BERR
Write to Clear
0
29⁽¹⁾
STER
Write to Clear
0
Description
Reserved: These bit positions are reserved for future
expansion.
ACK Error: Indicates an acknowledgement error.
‘1’ = Indicates that an acknowledgement error has occurred.
‘0’ = Indicates that an acknowledgement error has not occurred
on the bus since the last write to this register.
If this bit is set, writing a ‘1’ clears it.
Bit Error: Indicates that the received bit is not the same as the
transmitted bit during bus communication.
‘1’ = Indicates that a bit error has occurred.
‘0’ = Indicates that a bit error has not occurred on the bus since
the last write to this register.
If this bit is set, writing a ‘1’ clears it.
Stuff Error: Indicates an error if there is a stuffing violation.
‘1’ = Indicates that a stuff error has occurred.
‘0’ = Indicates that a stuff error has not occurred on the bus
since the last write to this register.
If this bit is set, writing a ‘1’ clears it.
1. In case of a CRC Error and a CRC delimiter corruption, only the FMER bit is set.
Status Register
The CAN Status Register provides a status of all conditions of the core. Specifically, FIFO status, Error State, Bus
State and Configuration mode are reported.
Status Register
Table 19 shows the SR bit positions in the SR and Table 20 provides SR bit descriptions.
Table 19: Status Register BIT Positions
0 — 19
Reserved
26
BBSY
20
ACFBSY
27
BIDLE
21
TXFLL
28
NORMAL
22
TXBFLL
29
SLEEP
23 — 24
ESTAT[1..0]
30
LBACK
25
ERRWRN
31
CONFIG
DS791 June 22, 2011
www.xilinx.com
19
Product Specification