DS791 Datasheet, PDF (37/46 Pages) Xilinx, Inc – LogiCORE IP AXI Controller

LogiCORE IP AXI Controller Area Network (axi_can) (v1.03.a)
I/O Constraints
I/O Standards
The pins that interface to the CAN PHY device have a 3.3 volt signal level interface. The following constraints can
be used, provided the device I/O Banking rules are followed.
# Select the I/O standards for the interface to the CAN PHY
INST "CAN_PHY_TX"
INST "CAN_PHY_RX"
IOSTANDARD = "LVTTL"
IOSTANDARD = "LVTTL"
Device Utilization and Performance Benchmarks
Core Performance
Table 40 shows example performance and resource utilization benchmarks for the Spartan®-6 FPGA
(xc6slx45t-2-fgg484 device).
Table 40: Performance and Resource Utilization Benchmarks for the Spartan-6 FPGA (xc6slx45t-2-fgg484)
Parameter Values
Device Resources
F_MAX (MHz)
AXI
F_MAX
2
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
4
4
8
8
8
8
8
8
8
8
8
8
16
16
16
16
16
16
16
16
16
16
0
374
553
794
74.582
1
405
648
866
68.474
2
311
651
896
79.930
3
394
654
878
78.616
4
386
648
864
72.427
0
378
561
805
61.755
1
398
664
893
76.383
2
385
667
897
73.089
3
389
670
891
74.974
4
393
664
886
74.438
0
368
585
826
71.058
1
403
680
895
74.789
2
384
683
909
71.235
3
392
686
912
82.597
4
365
680
902
77.042
0
391
601
848
69.959
1
402
696
919
83.605
2
411
699
925
75.120
3
401
678
905
73.228
4
430
696
905
69.832
DS791 June 22, 2011
www.xilinx.com
37
Product Specification