DS791 Datasheet, PDF (11/46 Pages) Xilinx, Inc – LogiCORE IP AXI Controller

LogiCORE IP AXI Controller Area Network (axi_can) (v1.03.a)
CAN_CLK
The range of CAN_CLK clock is 8-24 MHz.
The user determines whether a DCM or an external oscillator is used to generate the CAN_CLK. If an external
oscillator is used, it should meet the tolerance requirements specified in the ISO 11898-1, CAN 2.0A and CAN 2.0B
standards.
Reset Mechanism
Two different reset mechanisms are provided for the CAN controller. The S_AXI_ARESET_N input mentioned in
Table 1 acts as the system reset. Apart from the system reset, a software reset is provided through the SRST bit in the
SRR register. Both the software reset and the system reset, reset the complete CAN core (the Object Layer and the
Transfer Layer as shown in Figure 1).
Software Reset
The software reset can be enabled by writing a '1' to the SRST bit in the SRR Register. When a software reset is
asserted, all the configuration registers including the SRST bit in the SRR Register are reset to their default values.
Read/Write transactions can be performed starting at the next valid transaction window.
System Reset
The system reset can be enabled by driving a '0' on the S_AXI_ARESET_N input. All the configuration registers are
reset to their default values. Read/Write transactions cannot be performed when the S_AXI_ARESET_N input is '0'.
Exceptions
The contents of the acceptance filter mask registers and acceptance filter ID registers are not cleared when the
software reset or system reset is asserted.
Reset Synchronization
A reset synchronizer resets each clock domain in the core. Because of this, some latency exists between the assertion
of reset and the actual reset of the core.
DS791 June 22, 2011
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Product Specification