DS791 Datasheet, PDF (5/46 Pages) Xilinx, Inc – LogiCORE IP AXI Controller

LogiCORE IP AXI Controller Area Network (axi_can) (v1.03.a)
I/O Signals
The AXI CAN I/O signals are listed and described inTable 1
Table 1: I/O Signal Description
Port
Signal Name
Interface
Signal
Type
Initial
State
Description
AXI Global System Signals
P1
S_AXI_ACLK
AXI
I
N/A AXI Clock
P2
S_AXI_ARESET_N
AXI
I
N/A AXI Reset (active Low)
AXI Write Address Channel Signals
P3
S_AXI_AWADDR[C_S_
AXI_ADDR_WIDTH- 1:0]
AXI
AXI Write address. The write address
I
N/A bus gives the address of the write
transaction.
P4
S_AXI_AWVALID
Write address valid. This signal indicates
AXI
I
N/A that valid write address and control
information are available.
P5
S_AXI_AWREADY
Write address ready. This signal
AXI
O
N/A
indicates that the slave is ready to accept
an address and associated control
signals.
AXI Write Data Channel Signals
P6
S_AXI_WDATA[C_S_AXI_
DATA_WIDTH - 1: 0]
AXI
I
N/A Write Data
P7
S_AXI_WSTB[C_S_AXI_
DATA_WIDTH/8- 1:0]
AXI
I
N/A
Write strobes. This signal indicates
which byte lanes to update in memory.
P8
S_AXI_WVALID
Write valid. This signal indicates that
AXI
I
N/A valid write data and strobes are
available.
P9
S_AXI_WREADY
AXI
O
0x0
Write ready. This signal indicates that the
slave can accept the write data.
AXI Write Response Channel Signal
P10 S_AXI_BRESP[1:0]
Write response. This signal indicates the
status of the write transaction.
AXI
O
0x0 ^{“00“- OKAY}
“10“- SLVERR
“11“- DECERR
P11 S_AXI_BVALID
Write response valid. This signal
AXI
O
0x0 indicates that a valid write response is
available
P12 S_AXI_BREADY
Response ready. This signal indicates
AXI
I
0x1 that the master can accept the response
information
DS791 June 22, 2011
www.xilinx.com
5
Product Specification