DS791 Datasheet, PDF (18/46 Pages) Xilinx, Inc – LogiCORE IP AXI Controller

LogiCORE IP AXI Controller Area Network (axi_can) (v1.03.a)
Error Indication Registers
The Error Counter Register (ECR) and the Error Status Register (ESR) comprise the Error Indication Registers.
Error Counter Register
The ECR is a read-only register. Writes to the ECR have no effect. The value of the error counters in the register
reflect the values of the transmit and receive error counters in the CAN Protocol Engine Module (see Figure 2).
The following conditions reset the Transmit and Receive Error counters:
• When a '1' is written to the SRST bit in the SRR.
• When a '0' is written to the CEN bit in the SRR.
• When the CAN controller enters Bus Off state.
• During Bus Off recovery when the CAN controller enters Error Active state after 128 occurrences of 11
consecutive recessive bits.
When in Bus Off recovery, the Receive Error counter is advanced by 1 whenever a sequence of 11 consecutive
recessive bits is seen.
Table 15 shows the bit positions in the ECR and Table 16 provides ECR bit descriptions.
Table 15: Error Count Register BIT Positions
0 —15
16 — 23
Reserved
REC[7..0]
24 — 31
TEC[7..0]
Table 16: Error Count Register Bit Descriptions
Bit(s)
Name
Core Access
Default
Value
0–15
Reserved
Read Only
0
16–23
REC[7..0]
Read Only
0
24–31
TEC[7..0]
Read Only
0
Description
Reserved: These bit positions are reserved for future expansion.
Receive Error Counter: Indicates the value of the Receive Error
Counter
Transmit Error Counter: Indicates the value of the Transmit
Error Counter
DS791 June 22, 2011
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Product Specification